cir_shifter.vhd

来自「用vhdl语言实现2DPSK数字传输」· VHDL 代码 · 共 53 行

-- 16位循环右移位同步置数寄存器,译码器的组合;
library ieee;
use ieee.std_logic_1164.all;
	entity cir_shifter is
	port(data_high,data_low	:in std_logic_vector(15 downto 0);
		load,clk	:in std_logic;
--		sl_in,sr_in,reset,clk:in std_logic;
--		mode	:in std_logic_vector(1 downto 0);
		qout	:buffer std_logic_vector(7 downto 0));
end cir_shifter;

architecture behave of cir_shifter is
	signal ch,cl:std_logic;
	signal qh,ql: std_logic_vector(15 downto 0);
	signal hl:std_logic_vector(1 downto 0);
begin
	ch<=qh(1);
	cl<=ql(0);
	hl(1)<=ch;
	hl(0)<=cl;
	process(clk)
		begin
			if(clk'event and clk='1') then 
				if (load='0') then
					qh<=data_high;
					ql<=data_low;						--同步置数；
				else 
					qh<=ch&qh(15 downto 1);		--循环右移；
					ql<=cl&ql(15 downto 1);
				end if;
			end if;
	end process;
	
	process(clk)
	begin
	if(clk'event and clk='1') then
	case hl is
		when "00"=>
			qout<="00000000";
		when "01"=>
			qout<="00000001";
		when "10"=>
			qout<="00000010";
		when "11"=>
			qout<="00000011";
		when others=>
			qout<="00000000";
	end case;
	end if;
	end process;
end behave;