research.map.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(11) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(11): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 11 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(12) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(12): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 12 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(13) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(13): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 13 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(14) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(14): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 14 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(15) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(15): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 15 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(16) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(16): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 16 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "lock (null) test_pass_buffer_8bit.v(17) " "Info: (10265) Verilog HDL Module Instantiation information at test_pass_buffer_8bit.v(17): instance \"(null)\" connects port \"lock\" to an empty expression" {  } { { "test_pass_buffer_8bit.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 17 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pass_buffer test_pass_buffer_8bit:comb_6\|pass_buffer:comb_4 " "Info: Elaborating entity \"pass_buffer\" for hierarchy \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_4\"" {  } { { "test_pass_buffer_8bit.v" "comb_4" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/research/test_pass_buffer_8bit.v" 10 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_4\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_4\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_7\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_7\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_10\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_8\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_8\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_6\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_6\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_9\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_9\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "test_pass_buffer_8bit:comb_6\|pass_buffer:comb_5\|pass test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass " "Info: Duplicate register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_5\|pass\" merged to single register \"test_pass_buffer_8bit:comb_6\|pass_buffer:comb_11\|pass\"" {  } { { "../Creativity/pass_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|research\|key_buffer:comb_4\|state 4 0 " "Info: State machine \"\|research\|key_buffer:comb_4\|state\" contains 4 states and 0 state bits" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|research\|key_buffer:comb_4\|state " "Info: Selected Auto state machine encoding method for state machine \"\|research\|key_buffer:comb_4\|state\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|research\|key_buffer:comb_4\|state " "Info: Encoding result for state machine \"\|research\|key_buffer:comb_4\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key_buffer:comb_4\|state.s2 " "Info: Encoded state bit \"key_buffer:comb_4\|state.s2\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key_buffer:comb_4\|state.s3 " "Info: Encoded state bit \"key_buffer:comb_4\|state.s3\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key_buffer:comb_4\|state.s1 " "Info: Encoded state bit \"key_buffer:comb_4\|state.s1\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key_buffer:comb_4\|state.start " "Info: Encoded state bit \"key_buffer:comb_4\|state.start\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|research\|key_buffer:comb_4\|state.start 0000 " "Info: State \"\|research\|key_buffer:comb_4\|state.start\" uses code string \"0000\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|research\|key_buffer:comb_4\|state.s1 0011 " "Info: State \"\|research\|key_buffer:comb_4\|state.s1\" uses code string \"0011\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|research\|key_buffer:comb_4\|state.s3 0101 " "Info: State \"\|research\|key_buffer:comb_4\|state.s3\" uses code string \"0101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|research\|key_buffer:comb_4\|state.s2 1001 " "Info: State \"\|research\|key_buffer:comb_4\|state.s2\" uses code string \"1001\"" {  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}  } { { "../Creativity/key_buffer.v" "" { Text "E:/学习/基于工程/CPLD设计竞赛/工程/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "41 " "Info: Implemented 41 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "30 " "Info: Implemented 30 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 27 08:46:15 2007 " "Info: Processing ended: Sat Oct 27 08:46:15 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}