research.tan.rpt

用vhdl语言实现2DPSK数字传输

Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Oct 27 08:46:22 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off research -c research
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "key_buffer:comb_4|state.s2" as buffer
    Info: Detected ripple clock "test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass" as buffer
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "key_buffer:comb_4|state.s3" and destination register "key_buffer:comb_4|state.start"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.389 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4|state.s3'
            Info: 2: + IC(0.982 ns) + CELL(0.511 ns) = 1.493 ns; Loc. = LC_X10_Y4_N0; Fanout = 1; COMB Node = 'key_buffer:comb_4|state~96'
            Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.389 ns; Loc. = LC_X10_Y4_N1; Fanout = 2; REG Node = 'key_buffer:comb_4|state.start'
            Info: Total cell delay = 1.102 ns ( 46.13 % )
            Info: Total interconnect delay = 1.287 ns ( 53.87 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
                Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N1; Fanout = 2; REG Node = 'key_buffer:comb_4|state.start'
                Info: Total cell delay = 2.081 ns ( 54.49 % )
                Info: Total interconnect delay = 1.738 ns ( 45.51 % )
            Info: - Longest clock path from clock "clk" to source register is 3.819 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
                Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4|state.s3'
                Info: Total cell delay = 2.081 ns ( 54.49 % )
                Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "generate_led:comb_5|q[6]" and destination pin or register "test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1" for clock "clk" (Hold time is 4.802 ns)
    Info: + Largest clock skew is 7.317 ns
        Info: + Longest clock path from clock "clk" to destination register is 11.136 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N8; Fanout = 3; REG Node = 'key_buffer:comb_4|state.s2'
            Info: 3: + IC(0.887 ns) + CELL(1.294 ns) = 6.376 ns; Loc. = LC_X10_Y4_N9; Fanout = 17; REG Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass'
            Info: 4: + IC(3.842 ns) + CELL(0.918 ns) = 11.136 ns; Loc. = LC_X9_Y10_N3; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1'
            Info: Total cell delay = 4.669 ns ( 41.93 % )
            Info: Total interconnect delay = 6.467 ns ( 58.07 % )
        Info: - Shortest clock path from clock "clk" to source register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y7_N2; Fanout = 3; REG Node = 'generate_led:comb_5|q[6]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: - Micro clock to output delay of source is 0.376 ns
    Info: - Shortest register to register delay is 2.360 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N2; Fanout = 3; REG Node = 'generate_led:comb_5|q[6]'
        Info: 2: + IC(2.080 ns) + CELL(0.280 ns) = 2.360 ns; Loc. = LC_X9_Y10_N3; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_10|out1'
        Info: Total cell delay = 0.280 ns ( 11.86 % )
        Info: Total interconnect delay = 2.080 ns ( 88.14 % )
    Info: + Micro hold delay of destination is 0.221 ns
Info: tsu for register "generate_led:comb_5|q[1]" (data pin = "reset", clock pin = "clk") is 2.078 ns
    Info: + Longest pin to register delay is 5.564 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_43; Fanout = 8; PIN Node = 'reset'
        Info: 2: + IC(3.371 ns) + CELL(1.061 ns) = 5.564 ns; Loc. = LC_X9_Y7_N5; Fanout = 3; REG Node = 'generate_led:comb_5|q[1]'
        Info: Total cell delay = 2.193 ns ( 39.41 % )
        Info: Total interconnect delay = 3.371 ns ( 60.59 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X9_Y7_N5; Fanout = 3; REG Node = 'generate_led:comb_5|q[1]'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: tco from clock "clk" to destination pin "led_out[7]" through register "test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1" is 15.041 ns
    Info: + Longest clock path from clock "clk" to source register is 11.136 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N8; Fanout = 3; REG Node = 'key_buffer:comb_4|state.s2'
        Info: 3: + IC(0.887 ns) + CELL(1.294 ns) = 6.376 ns; Loc. = LC_X10_Y4_N9; Fanout = 17; REG Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|pass'
        Info: 4: + IC(3.842 ns) + CELL(0.918 ns) = 11.136 ns; Loc. = LC_X10_Y10_N1; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1'
        Info: Total cell delay = 4.669 ns ( 41.93 % )
        Info: Total interconnect delay = 6.467 ns ( 58.07 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.529 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N1; Fanout = 1; REG Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|out1'
        Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X10_Y10_N1; Fanout = 1; COMB Node = 'test_pass_buffer_8bit:comb_6|pass_buffer:comb_11|dout~12'
        Info: 3: + IC(0.612 ns) + CELL(2.322 ns) = 3.529 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'led_out[7]'
        Info: Total cell delay = 2.917 ns ( 82.66 % )
        Info: Total interconnect delay = 0.612 ns ( 17.34 % )
Info: th for register "key_buffer:comb_4|state.s3" (data pin = "change", clock pin = "clk") is -1.209 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4|state.s3'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.249 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 4; PIN Node = 'change'
        Info: 2: + IC(3.056 ns) + CELL(1.061 ns) = 5.249 ns; Loc. = LC_X10_Y4_N4; Fanout = 2; REG Node = 'key_buffer:comb_4|state.s3'
        Info: Total cell delay = 2.193 ns ( 41.78 % )
        Info: Total interconnect delay = 3.056 ns ( 58.22 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Sat Oct 27 08:46:22 2007
    Info: Elapsed time: 00:00:01