phase_table.mif

用vhdl语言实现2DPSK数字传输

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- Quartus II generated Memory Initialization File (.mif)

WIDTH=8;
DEPTH=32;

ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;

CONTENT BEGIN
	0   :   127;
	1   :   152;
	2   :   176;
	3   :   198;
	4   :   218;
	5   :   233;
	6   :   245;
	7   :   252;
	8   :   255;
	9   :   253;
	10  :   245;
	11  :   233;
	12  :   218;
	13  :   198;
	14  :   176;
	15  :   152;
	16  :   127;
	17  :   103;
	18  :   79;
	19  :   57;
	20  :   37;
	21  :   21;
	22  :   10;
	23  :   2;
	24  :   0;
	25  :   2;
	26  :   10;
	27  :   21;
	28  :   37;
	29  :   57;
	30  :   79;
	31  :   103;
END;