prev_cmp_dpsk.fit.qmsg

用vhdl语言实现2DPSK数字传输

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:01 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:01" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.928 ns register pin " "Info: Estimated most critical path is register to pin delay of 5.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|out1 1 REG LAB_X4_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y7; Fanout = 1; REG Node = 'DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|out1'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|out1 } "NODE_NAME" } } { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|dout~13 2 COMB LAB_X4_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LAB_X4_Y7; Fanout = 1; COMB Node = 'DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|dout~13'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|out1 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|dout~13 } "NODE_NAME" } } { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.011 ns) + CELL(2.322 ns) 5.928 ns led_light\[7\] 3 PIN PIN_122 0 " "Info: 3: + IC(3.011 ns) + CELL(2.322 ns) = 5.928 ns; Loc. = PIN_122; Fanout = 0; PIN Node = 'led_light\[7\]'" {  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.333 ns" { DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|dout~13 led_light[7] } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 248 408 584 264 "led_light\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.917 ns ( 49.21 % ) " "Info: Total cell delay = 2.917 ns ( 49.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.011 ns ( 50.79 % ) " "Info: Total interconnect delay = 3.011 ns ( 50.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.928 ns" { DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|out1 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|dout~13 led_light[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}