dpsk.hier_info

用vhdl语言实现2DPSK数字传输

clk_50MHz => qa[3].CLK
clk_50MHz => qa[2].CLK
clk_50MHz => qa[1].CLK
clk_50MHz => qa[0].CLK
clk_phase <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
clk_lcd <= Equal1.DB_MAX_OUTPUT_PORT_TYPE
clk_diff <= Equal2.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|key_buffer:comb_6
clk => state~4.IN1
key_in => state~3.OUTPUTSELECT
key_in => state~2.OUTPUTSELECT
key_in => state~1.OUTPUTSELECT
key_in => state.start.DATAIN
key_out <= state.s2.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|generate_a:comb_7
reset => q~7.OUTPUTSELECT
reset => q~6.OUTPUTSELECT
reset => q~5.OUTPUTSELECT
reset => q~4.OUTPUTSELECT
reset => q~3.OUTPUTSELECT
reset => q~2.OUTPUTSELECT
reset => q~1.OUTPUTSELECT
reset => q~0.OUTPUTSELECT
clk_m => q[7].CLK
clk_m => q[6].CLK
clk_m => q[5].CLK
clk_m => q[4].CLK
clk_m => q[3].CLK
clk_m => q[2].CLK
clk_m => q[1].CLK
clk_m => q[0].CLK
qm <= q[0].DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|generate_m:comb_8
reset => q~11.OUTPUTSELECT
reset => q~10.OUTPUTSELECT
reset => q~9.OUTPUTSELECT
reset => q~8.OUTPUTSELECT
reset => q~7.OUTPUTSELECT
reset => q~6.OUTPUTSELECT
reset => q~5.OUTPUTSELECT
reset => q~4.OUTPUTSELECT
reset => q~3.OUTPUTSELECT
reset => q~2.OUTPUTSELECT
reset => q~1.OUTPUTSELECT
reset => q~0.OUTPUTSELECT
clk_m => q[11].CLK
clk_m => q[10].CLK
clk_m => q[9].CLK
clk_m => q[8].CLK
clk_m => q[7].CLK
clk_m => q[6].CLK
clk_m => q[5].CLK
clk_m => q[4].CLK
clk_m => q[3].CLK
clk_m => q[2].CLK
clk_m => q[1].CLK
clk_m => q[0].CLK
qm <= q[0].DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|channel_choice:u1
channel => Decoder0.IN0
d_int => q~0.DATAA
d_ext => q~0.DATAB
q <= q~0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|channel_choice:u2
channel => Decoder0.IN0
d_int => q~0.DATAA
d_ext => q~0.DATAB
q <= q~0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|modulate:comb_9
a => a~0.IN1
clk_phase => clk_phase~0.IN2
clk_dig => clk_dig~0.IN1
phase_out[0] <= phase_table:comb_11.qout
phase_out[1] <= phase_table:comb_11.qout
phase_out[2] <= phase_table:comb_11.qout
phase_out[3] <= phase_table:comb_11.qout
phase_out[4] <= phase_table:comb_11.qout
phase_out[5] <= phase_table:comb_11.qout
phase_out[6] <= phase_table:comb_11.qout
phase_out[7] <= phase_table:comb_11.qout
phase_state[0] <= s[0].DB_MAX_OUTPUT_PORT_TYPE
phase_state[1] <= s[1].DB_MAX_OUTPUT_PORT_TYPE
phase_state[2] <= s[2].DB_MAX_OUTPUT_PORT_TYPE
phase_state[3] <= s[3].DB_MAX_OUTPUT_PORT_TYPE
phase_state[4] <= s[4].DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|modulate:comb_9|diff_code:comb_9
a => comb~0.IN1
clk => clk~0.IN1
b <= my_dff:comb_6.q


|DPSK|DPSK_shell:inst|modulate:comb_9|diff_code:comb_9|my_dff:comb_6
clk => q~reg0.CLK
clk => qb~reg0.CLK
d => q~reg0.DATAIN
d => qb~reg0.DATAIN
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
qb <= qb~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10
clk => clk~0.IN1
clr => clr~0.IN1
syn => comb~0.IN1
s[0] <= my_syn_counter:comb_10.q
s[1] <= my_syn_counter:comb_10.q
s[2] <= my_syn_counter:comb_10.q
s[3] <= my_syn_counter:comb_10.q
s[4] <= comb~0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clr => q~9.OUTPUTSELECT
clr => q~8.OUTPUTSELECT
clr => q~7.OUTPUTSELECT
clr => q~6.OUTPUTSELECT
clr => q~5.OUTPUTSELECT
load => q~4.OUTPUTSELECT
load => q~3.OUTPUTSELECT
load => q~2.OUTPUTSELECT
load => q~1.OUTPUTSELECT
load => q~0.OUTPUTSELECT
d[0] => q~4.DATAB
d[1] => q~3.DATAB
d[2] => q~2.DATAB
d[3] => q~1.DATAB
d[4] => q~0.DATAB
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cin <= Equal0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|modulate:comb_9|phase_table:comb_11
clk => qout[7]~reg0.CLK
clk => qout[6]~reg0.CLK
clk => qout[5]~reg0.CLK
clk => qout[4]~reg0.CLK
clk => qout[3]~reg0.CLK
clk => qout[2]~reg0.CLK
clk => qout[1]~reg0.CLK
clk => qout[0]~reg0.CLK
address[0] => Ram0.RADDR
address[1] => Ram0.RADDR1
address[2] => Ram0.RADDR2
address[3] => Ram0.RADDR3
address[4] => Ram0.RADDR4
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|demodulate:comb_10
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
din => din~0.IN1
dout <= shift_detect:comb_4.a


|DPSK|DPSK_shell:inst|demodulate:comb_10|shift_detect:comb_4
clk => clk~0.IN1
m1 => m1~0.IN1
a <= comb~0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|demodulate:comb_10|shift_detect:comb_4|my_shift_reg:comb_6
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
d => q[4]~reg0.DATAIN
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|key_buffer:comb_11
clk => state~4.IN1
key_in => state~3.OUTPUTSELECT
key_in => state~2.OUTPUTSELECT
key_in => state~1.OUTPUTSELECT
key_in => state.start.DATAIN
key_out <= state.s2.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer:u5
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer:u6
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7
change => change~0.IN8
din[0] => din[0]~7.IN1
din[1] => din[1]~6.IN1
din[2] => din[2]~5.IN1
din[3] => din[3]~4.IN1
din[4] => din[4]~3.IN1
din[5] => din[5]~2.IN1
din[6] => din[6]~1.IN1
din[7] => din[7]~0.IN1
dout[0] <= pass_buffer:comb_4.dout
dout[1] <= pass_buffer:comb_5.dout
dout[2] <= pass_buffer:comb_6.dout
dout[3] <= pass_buffer:comb_7.dout
dout[4] <= pass_buffer:comb_8.dout
dout[5] <= pass_buffer:comb_9.dout
dout[6] <= pass_buffer:comb_10.dout
dout[7] <= pass_buffer:comb_11.dout
lock <= pass_buffer:comb_4.lock


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_5
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_6
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_7
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_8
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_9
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_10
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11
change => pass.CLK
din => out1.DATAIN
din => dout~0.IN1
dout <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
lock <= pass.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|dig_display:u3
a => Decoder0.IN0
dig_code[0] <= <GND>
dig_code[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dig_code[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dig_code[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dig_code[4] <= <VCC>
dig_code[5] <= <VCC>
dig_code[6] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|dig_display:u4
a => Decoder0.IN0
dig_code[0] <= <GND>
dig_code[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dig_code[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dig_code[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
dig_code[4] <= <VCC>
dig_code[5] <= <VCC>
dig_code[6] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|LCM_pre:comb_12
reset => reset~0.IN1
clk_lcm_buf => clk_lcm_buf~0.IN2
clk_lcd_base => wave_low[1].CLK
clk_lcd_base => wave_low[0].CLK
clk_lcd_base => wave_low1[1].CLK
clk_lcd_base => wave_low1[0].CLK
clk_lcd_base => clk_ser~0.IN0
lock => lock~0.IN1
wave_in[0] => Decoder0.IN4
wave_in[1] => Decoder0.IN3
wave_in[2] => Decoder0.IN2
wave_in[3] => Decoder0.IN1
wave_in[4] => Decoder0.IN0
reset_pre <= key_buffer:comb_42.key_out
clk_ser <= clk_ser~0.DB_MAX_OUTPUT_PORT_TYPE
lock_pre <= key_buffer:comb_43.key_out
wave_out[0] <= wave_low[0].DB_MAX_OUTPUT_PORT_TYPE
wave_out[1] <= wave_low[1].DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42
clk => state~4.IN1
key_in => state~3.OUTPUTSELECT
key_in => state~2.OUTPUTSELECT
key_in => state~1.OUTPUTSELECT
key_in => state.start.DATAIN
key_out <= state.s2.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_43
clk => state~4.IN1
key_in => state~3.OUTPUTSELECT
key_in => state~2.OUTPUTSELECT
key_in => state~1.OUTPUTSELECT
key_in => state.start.DATAIN
key_out <= state.s2.DB_MAX_OUTPUT_PORT_TYPE