dpsk.hier_info

用vhdl语言实现2DPSK数字传输

|DPSK
RW <= lcdcont:inst1.rw_out
reset => DPSK_shell:inst.reset
clk_50MHz => DPSK_shell:inst.clk_50MHz
clk_50MHz => lcdcont:inst1.clk
din_m2 => DPSK_shell:inst.din_m2
din_a2 => DPSK_shell:inst.din_a2
channel_choide_a => DPSK_shell:inst.channel_choice_a
channel_choice_m => DPSK_shell:inst.channel_choice_m
change => DPSK_shell:inst.change
cont <= lcdcont:inst1.cont
RS <= lcdcont:inst1.select_out
E <= lcdcont:inst1.enable_out
dout <= DPSK_shell:inst.dout
dout_a1 <= DPSK_shell:inst.dout_a1
dig_code_d[0] <= DPSK_shell:inst.dig_code_d[0]
dig_code_d[1] <= DPSK_shell:inst.dig_code_d[1]
dig_code_d[2] <= DPSK_shell:inst.dig_code_d[2]
dig_code_d[3] <= DPSK_shell:inst.dig_code_d[3]
dig_code_d[4] <= DPSK_shell:inst.dig_code_d[4]
dig_code_d[5] <= DPSK_shell:inst.dig_code_d[5]
dig_code_d[6] <= DPSK_shell:inst.dig_code_d[6]
dig_code_m[0] <= DPSK_shell:inst.dig_code_m[0]
dig_code_m[1] <= DPSK_shell:inst.dig_code_m[1]
dig_code_m[2] <= DPSK_shell:inst.dig_code_m[2]
dig_code_m[3] <= DPSK_shell:inst.dig_code_m[3]
dig_code_m[4] <= DPSK_shell:inst.dig_code_m[4]
dig_code_m[5] <= DPSK_shell:inst.dig_code_m[5]
dig_code_m[6] <= DPSK_shell:inst.dig_code_m[6]
lcm_out[0] <= lcdcont:inst1.data_out[0]
lcm_out[1] <= lcdcont:inst1.data_out[1]
lcm_out[2] <= lcdcont:inst1.data_out[2]
lcm_out[3] <= lcdcont:inst1.data_out[3]
lcm_out[4] <= lcdcont:inst1.data_out[4]
lcm_out[5] <= lcdcont:inst1.data_out[5]
lcm_out[6] <= lcdcont:inst1.data_out[6]
lcm_out[7] <= lcdcont:inst1.data_out[7]
led_light[0] <= DPSK_shell:inst.led_light[0]
led_light[1] <= DPSK_shell:inst.led_light[1]
led_light[2] <= DPSK_shell:inst.led_light[2]
led_light[3] <= DPSK_shell:inst.led_light[3]
led_light[4] <= DPSK_shell:inst.led_light[4]
led_light[5] <= DPSK_shell:inst.led_light[5]
led_light[6] <= DPSK_shell:inst.led_light[6]
led_light[7] <= DPSK_shell:inst.led_light[7]
phase_out[0] <= DPSK_shell:inst.phase_out[0]
phase_out[1] <= DPSK_shell:inst.phase_out[1]
phase_out[2] <= DPSK_shell:inst.phase_out[2]
phase_out[3] <= DPSK_shell:inst.phase_out[3]
phase_out[4] <= DPSK_shell:inst.phase_out[4]
phase_out[5] <= DPSK_shell:inst.phase_out[5]
phase_out[6] <= DPSK_shell:inst.phase_out[6]
phase_out[7] <= DPSK_shell:inst.phase_out[7]


|DPSK|lcdcont:inst1
lock => low[0].ENA
lock => low[1].ENA
lock => low[2].ENA
lock => low[3].ENA
lock => low[4].ENA
lock => low[5].ENA
lock => low[6].ENA
lock => low[7].ENA
lock => low[8].ENA
lock => low[9].ENA
lock => low[10].ENA
lock => low[11].ENA
lock => low[12].ENA
lock => low[13].ENA
lock => low[14].ENA
lock => low[15].ENA
lock => high[0].ENA
lock => high[1].ENA
lock => high[2].ENA
lock => high[3].ENA
lock => high[4].ENA
lock => high[5].ENA
lock => high[6].ENA
lock => high[7].ENA
lock => high[8].ENA
lock => high[9].ENA
lock => high[10].ENA
lock => high[11].ENA
lock => high[12].ENA
lock => high[13].ENA
lock => high[14].ENA
lock => high[15].ENA
clk => clockdiv:div.clockin
ser_clk => shifter:myshift_low.clk
ser_clk => shifter:myshift_high.clk
reset => shifter:myshift_low.reset
reset => shifter:myshift_high.reset
reset => lcd:mylcd.reset
reset => valid_int.PRESET
ser_in[0] => shifter:myshift_low.sr_in
ser_in[1] => shifter:myshift_high.sr_in
data_out[0] <= lcd:mylcd.lcd_data[0]
data_out[1] <= lcd:mylcd.lcd_data[1]
data_out[2] <= lcd:mylcd.lcd_data[2]
data_out[3] <= lcd:mylcd.lcd_data[3]
data_out[4] <= lcd:mylcd.lcd_data[4]
data_out[5] <= lcd:mylcd.lcd_data[5]
data_out[6] <= lcd:mylcd.lcd_data[6]
data_out[7] <= lcd:mylcd.lcd_data[7]
rw_out <= lcd:mylcd.lcd_rw
cont <= <GND>
select_out <= lcd:mylcd.lcd_select
enable_out <= lcd:mylcd.lcd_enable
clk_lcm_buf <= clockdiv:div.clockout


|DPSK|lcdcont:inst1|lcd:mylcd
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => write_mode.CLK
clk => lcd_select~reg0.CLK
clk => rw_int.CLK
clk => done~reg0.CLK
clk => lcd_data[7]~reg0.CLK
clk => lcd_data[6]~reg0.CLK
clk => lcd_data[5]~reg0.CLK
clk => lcd_data[4]~reg0.CLK
clk => lcd_data[3]~reg0.CLK
clk => lcd_data[2]~reg0.CLK
clk => lcd_data[1]~reg0.CLK
clk => lcd_data[0]~reg0.CLK
clk => last_data_valid.CLK
clk => lcd_enable.DATAIN
clk => state~9.IN1
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => write_mode.PRESET
reset => last_data_valid.ENA
reset => lcd_select~reg0.ENA
reset => rw_int.ENA
reset => done~reg0.ENA
reset => lcd_data[7]~reg0.ENA
reset => lcd_data[6]~reg0.ENA
reset => lcd_data[5]~reg0.ENA
reset => lcd_data[4]~reg0.ENA
reset => lcd_data[3]~reg0.ENA
reset => lcd_data[2]~reg0.ENA
reset => lcd_data[1]~reg0.ENA
reset => lcd_data[0]~reg0.ENA
reset => state~10.IN1
data_valid => last_data_valid~0.OUTPUTSELECT
data_valid => state_set~0.IN1
high[0] => Mux10.IN15
high[1] => Mux10.IN14
high[2] => Mux10.IN13
high[3] => Mux10.IN12
high[4] => Mux10.IN11
high[5] => Mux10.IN10
high[6] => Mux10.IN9
high[7] => Mux10.IN8
high[8] => Mux10.IN7
high[9] => Mux10.IN6
high[10] => Mux10.IN5
high[11] => Mux10.IN4
high[12] => Mux10.IN3
high[13] => Mux10.IN2
high[14] => Mux10.IN1
high[15] => Mux10.IN0
low[0] => Mux11.IN15
low[1] => Mux11.IN14
low[2] => Mux11.IN13
low[3] => Mux11.IN12
low[4] => Mux11.IN11
low[5] => Mux11.IN10
low[6] => Mux11.IN9
low[7] => Mux11.IN8
low[8] => Mux11.IN7
low[9] => Mux11.IN6
low[10] => Mux11.IN5
low[11] => Mux11.IN4
low[12] => Mux11.IN3
low[13] => Mux11.IN2
low[14] => Mux11.IN1
low[15] => Mux11.IN0
lcd_data[0] <= lcd_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[1] <= lcd_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[2] <= lcd_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[3] <= lcd_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[4] <= lcd_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[5] <= lcd_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[6] <= lcd_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_data[7] <= lcd_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_select <= lcd_select~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= rw_int.DB_MAX_OUTPUT_PORT_TYPE
tt <= <GND>
lcd_enable <= clk.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|lcdcont:inst1|clockdiv:div
clockin => \count:counter[14].CLK
clockin => \count:counter[13].CLK
clockin => \count:counter[12].CLK
clockin => \count:counter[11].CLK
clockin => \count:counter[10].CLK
clockin => \count:counter[9].CLK
clockin => \count:counter[8].CLK
clockin => \count:counter[7].CLK
clockin => \count:counter[6].CLK
clockin => \count:counter[5].CLK
clockin => \count:counter[4].CLK
clockin => \count:counter[3].CLK
clockin => \count:counter[2].CLK
clockin => \count:counter[1].CLK
clockin => \count:counter[0].CLK
clockin => clock_int.CLK
clockout <= clock_int.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|lcdcont:inst1|shifter:myshift_high
reset => qout~15.OUTPUTSELECT
reset => qout~14.OUTPUTSELECT
reset => qout~13.OUTPUTSELECT
reset => qout~12.OUTPUTSELECT
reset => qout~11.OUTPUTSELECT
reset => qout~10.OUTPUTSELECT
reset => qout~9.OUTPUTSELECT
reset => qout~8.OUTPUTSELECT
reset => qout~7.OUTPUTSELECT
reset => qout~6.OUTPUTSELECT
reset => qout~5.OUTPUTSELECT
reset => qout~4.OUTPUTSELECT
reset => qout~3.OUTPUTSELECT
reset => qout~2.OUTPUTSELECT
reset => qout~1.OUTPUTSELECT
reset => qout~0.OUTPUTSELECT
sr_in => qout~0.DATAA
clk => qout[15]~reg0.CLK
clk => qout[14]~reg0.CLK
clk => qout[13]~reg0.CLK
clk => qout[12]~reg0.CLK
clk => qout[11]~reg0.CLK
clk => qout[10]~reg0.CLK
clk => qout[9]~reg0.CLK
clk => qout[8]~reg0.CLK
clk => qout[7]~reg0.CLK
clk => qout[6]~reg0.CLK
clk => qout[5]~reg0.CLK
clk => qout[4]~reg0.CLK
clk => qout[3]~reg0.CLK
clk => qout[2]~reg0.CLK
clk => qout[1]~reg0.CLK
clk => qout[0]~reg0.CLK
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[8] <= qout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[9] <= qout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[10] <= qout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[11] <= qout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[12] <= qout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[13] <= qout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[14] <= qout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[15] <= qout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|lcdcont:inst1|shifter:myshift_low
reset => qout~15.OUTPUTSELECT
reset => qout~14.OUTPUTSELECT
reset => qout~13.OUTPUTSELECT
reset => qout~12.OUTPUTSELECT
reset => qout~11.OUTPUTSELECT
reset => qout~10.OUTPUTSELECT
reset => qout~9.OUTPUTSELECT
reset => qout~8.OUTPUTSELECT
reset => qout~7.OUTPUTSELECT
reset => qout~6.OUTPUTSELECT
reset => qout~5.OUTPUTSELECT
reset => qout~4.OUTPUTSELECT
reset => qout~3.OUTPUTSELECT
reset => qout~2.OUTPUTSELECT
reset => qout~1.OUTPUTSELECT
reset => qout~0.OUTPUTSELECT
sr_in => qout~0.DATAA
clk => qout[15]~reg0.CLK
clk => qout[14]~reg0.CLK
clk => qout[13]~reg0.CLK
clk => qout[12]~reg0.CLK
clk => qout[11]~reg0.CLK
clk => qout[10]~reg0.CLK
clk => qout[9]~reg0.CLK
clk => qout[8]~reg0.CLK
clk => qout[7]~reg0.CLK
clk => qout[6]~reg0.CLK
clk => qout[5]~reg0.CLK
clk => qout[4]~reg0.CLK
clk => qout[3]~reg0.CLK
clk => qout[2]~reg0.CLK
clk => qout[1]~reg0.CLK
clk => qout[0]~reg0.CLK
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[4] <= qout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[5] <= qout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[6] <= qout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[7] <= qout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[8] <= qout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[9] <= qout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[10] <= qout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[11] <= qout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[12] <= qout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[13] <= qout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[14] <= qout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[15] <= qout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DPSK|DPSK_shell:inst
clk_50MHz => clk_50MHz~0.IN1
din_a2 => din_a2~0.IN1
din_m2 => din_m2~0.IN1
phase_out[0] <= phase_out[0]~7.DB_MAX_OUTPUT_PORT_TYPE
phase_out[1] <= phase_out[1]~6.DB_MAX_OUTPUT_PORT_TYPE
phase_out[2] <= phase_out[2]~5.DB_MAX_OUTPUT_PORT_TYPE
phase_out[3] <= phase_out[3]~4.DB_MAX_OUTPUT_PORT_TYPE
phase_out[4] <= phase_out[4]~3.DB_MAX_OUTPUT_PORT_TYPE
phase_out[5] <= phase_out[5]~2.DB_MAX_OUTPUT_PORT_TYPE
phase_out[6] <= phase_out[6]~1.DB_MAX_OUTPUT_PORT_TYPE
phase_out[7] <= phase_out[7]~0.DB_MAX_OUTPUT_PORT_TYPE
dout <= dout~0.DB_MAX_OUTPUT_PORT_TYPE
change => change~0.IN2
channel_choice_a => channel_choice_a~0.IN1
channel_choice_m => channel_choice_m~0.IN1
dout_a1 <= din_a1.DB_MAX_OUTPUT_PORT_TYPE
dig_code_m[0] <= dig_display:u3.dig_code
dig_code_m[1] <= dig_display:u3.dig_code
dig_code_m[2] <= dig_display:u3.dig_code
dig_code_m[3] <= dig_display:u3.dig_code
dig_code_m[4] <= dig_display:u3.dig_code
dig_code_m[5] <= dig_display:u3.dig_code
dig_code_m[6] <= dig_display:u3.dig_code
dig_code_d[0] <= dig_display:u4.dig_code
dig_code_d[1] <= dig_display:u4.dig_code
dig_code_d[2] <= dig_display:u4.dig_code
dig_code_d[3] <= dig_display:u4.dig_code
dig_code_d[4] <= dig_display:u4.dig_code
dig_code_d[5] <= dig_display:u4.dig_code
dig_code_d[6] <= dig_display:u4.dig_code
led_light[0] <= pass_buffer_8bit:u7.dout
led_light[1] <= pass_buffer_8bit:u7.dout
led_light[2] <= pass_buffer_8bit:u7.dout
led_light[3] <= pass_buffer_8bit:u7.dout
led_light[4] <= pass_buffer_8bit:u7.dout
led_light[5] <= pass_buffer_8bit:u7.dout
led_light[6] <= pass_buffer_8bit:u7.dout
led_light[7] <= pass_buffer_8bit:u7.dout
clk_lcm_buf => clk_lcm_buf~0.IN1
reset => reset~0.IN2
reset_pre <= LCM_pre:comb_12.reset_pre
clk_ser <= LCM_pre:comb_12.clk_ser
lock_pre <= LCM_pre:comb_12.lock_pre
wave_out[0] <= LCM_pre:comb_12.wave_out
wave_out[1] <= LCM_pre:comb_12.wave_out


|DPSK|DPSK_shell:inst|clk_div:comb_5
clk_50MHz => qa[8].CLK
clk_50MHz => qa[7].CLK
clk_50MHz => qa[6].CLK
clk_50MHz => qa[5].CLK
clk_50MHz => qa[4].CLK