dpsk.map.qmsg

用vhdl语言实现2DPSK数字传输

{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "DPSK_shell.v(62) " "Critical Warning (10846): Verilog HDL Instantiation warning at DPSK_shell.v(62): instance has no name" {  } { { "../Creativity/DPSK_shell.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 62 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DPSK " "Info: Elaborating entity \"DPSK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcdcont lcdcont:inst1 " "Info: Elaborating entity \"lcdcont\" for hierarchy \"lcdcont:inst1\"" {  } { { "DPSK.bdf" "inst1" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { -56 120 352 104 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset lcdcont.vhd(75) " "Warning (10492): VHDL Process Statement warning at lcdcont.vhd(75): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../Creativity/lcdcont.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 75 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcdcont:inst1\|lcd:mylcd " "Info: Elaborating entity \"lcd\" for hierarchy \"lcdcont:inst1\|lcd:mylcd\"" {  } { { "../Creativity/lcdcont.vhd" "mylcd" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 94 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clockdiv lcdcont:inst1\|clockdiv:div " "Info: Elaborating entity \"clockdiv\" for hierarchy \"lcdcont:inst1\|clockdiv:div\"" {  } { { "../Creativity/lcdcont.vhd" "div" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 108 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shifter lcdcont:inst1\|shifter:myshift_high " "Info: Elaborating entity \"shifter\" for hierarchy \"lcdcont:inst1\|shifter:myshift_high\"" {  } { { "../Creativity/lcdcont.vhd" "myshift_high" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 112 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DPSK_shell DPSK_shell:inst " "Info: Elaborating entity \"DPSK_shell\" for hierarchy \"DPSK_shell:inst\"" {  } { { "DPSK.bdf" "inst" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 160 120 352 384 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div DPSK_shell:inst\|clk_div:comb_5 " "Info: Elaborating entity \"clk_div\" for hierarchy \"DPSK_shell:inst\|clk_div:comb_5\"" {  } { { "../Creativity/DPSK_shell.v" "comb_5" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 clk_div.v(26) " "Warning (10230): Verilog HDL assignment warning at clk_div.v(26): truncated value with size 32 to match size of target (9)" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clk_div.v(32) " "Warning (10230): Verilog HDL assignment warning at clk_div.v(32): truncated value with size 32 to match size of target (3)" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clk_div.v(38) " "Warning (10230): Verilog HDL assignment warning at clk_div.v(38): truncated value with size 32 to match size of target (3)" {  } { { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_buffer DPSK_shell:inst\|key_buffer:comb_6 " "Info: Elaborating entity \"key_buffer\" for hierarchy \"DPSK_shell:inst\|key_buffer:comb_6\"" {  } { { "../Creativity/DPSK_shell.v" "comb_6" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 40 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generate_a DPSK_shell:inst\|generate_a:comb_7 " "Info: Elaborating entity \"generate_a\" for hierarchy \"DPSK_shell:inst\|generate_a:comb_7\"" {  } { { "../Creativity/DPSK_shell.v" "comb_7" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generate_m DPSK_shell:inst\|generate_m:comb_8 " "Info: Elaborating entity \"generate_m\" for hierarchy \"DPSK_shell:inst\|generate_m:comb_8\"" {  } { { "../Creativity/DPSK_shell.v" "comb_8" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 42 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "channel_choice DPSK_shell:inst\|channel_choice:u1 " "Info: Elaborating entity \"channel_choice\" for hierarchy \"DPSK_shell:inst\|channel_choice:u1\"" {  } { { "../Creativity/DPSK_shell.v" "u1" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 44 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "modulate DPSK_shell:inst\|modulate:comb_9 " "Info: Elaborating entity \"modulate\" for hierarchy \"DPSK_shell:inst\|modulate:comb_9\"" {  } { { "../Creativity/DPSK_shell.v" "comb_9" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/DPSK_shell.v" 47 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "diff_code DPSK_shell:inst\|modulate:comb_9\|diff_code:comb_9 " "Info: Elaborating entity \"diff_code\" for hierarchy \"DPSK_shell:inst\|modulate:comb_9\|diff_code:comb_9\"" {  } { { "../Creativity/modulate.v" "comb_9" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/modulate.v" 15 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_dff DPSK_shell:inst\|modulate:comb_9\|diff_code:comb_9\|my_dff:comb_6 " "Info: Elaborating entity \"my_dff\" for hierarchy \"DPSK_shell:inst\|modulate:comb_9\|diff_code:comb_9\|my_dff:comb_6\"" {  } { { "../Creativity/diff_code.v" "comb_6" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/diff_code.v" 8 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_counter DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10 " "Info: Elaborating entity \"phase_counter\" for hierarchy \"DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\"" {  } { { "../Creativity/modulate.v" "comb_10" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/modulate.v" 16 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_syn_counter DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10 " "Info: Elaborating entity \"my_syn_counter\" for hierarchy \"DPSK_shell:inst\|modulate:comb_9\|phase_counter:comb_10\|my_syn_counter:comb_10\"" {  } { { "../Creativity/phase_counter.v" "comb_10" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_counter.v" 13 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 my_syn_counter.v(15) " "Warning (10230): Verilog HDL assignment warning at my_syn_counter.v(15): truncated value with size 32 to match size of target (5)" {  } { { "../Creativity/my_syn_counter.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/my_syn_counter.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_table DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11 " "Info: Elaborating entity \"phase_table\" for hierarchy \"DPSK_shell:inst\|modulate:comb_9\|phase_table:comb_11\"" {  } { { "../Creativity/modulate.v" "comb_11" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/modulate.v" 17 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}