📄 prev_cmp_dpsk.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50MHz register lcdcont:inst1\|shifter:myshift_high\|qout\[8\] register lcdcont:inst1\|high\[8\] 48.09 MHz 20.795 ns Internal " "Info: Clock \"clk_50MHz\" has Internal fmax of 48.09 MHz between source register \"lcdcont:inst1\|shifter:myshift_high\|qout\[8\]\" and destination register \"lcdcont:inst1\|high\[8\]\" (period= 20.795 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.337 ns + Longest register register " "Info: + Longest register to register delay is 2.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcdcont:inst1\|shifter:myshift_high\|qout\[8\] 1 REG LC_X14_Y7_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y7_N9; Fanout = 2; REG Node = 'lcdcont:inst1\|shifter:myshift_high\|qout\[8\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcdcont:inst1|shifter:myshift_high|qout[8] } "NODE_NAME" } } { "../LCD/lcd_zifu/shifter.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/shifter.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.057 ns) + CELL(0.280 ns) 2.337 ns lcdcont:inst1\|high\[8\] 2 REG LC_X13_Y6_N2 1 " "Info: 2: + IC(2.057 ns) + CELL(0.280 ns) = 2.337 ns; Loc. = LC_X13_Y6_N2; Fanout = 1; REG Node = 'lcdcont:inst1\|high\[8\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.337 ns" { lcdcont:inst1|shifter:myshift_high|qout[8] lcdcont:inst1|high[8] } "NODE_NAME" } } { "../Creativity/lcdcont.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 11.98 % ) " "Info: Total cell delay = 0.280 ns ( 11.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.057 ns ( 88.02 % ) " "Info: Total interconnect delay = 2.057 ns ( 88.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.337 ns" { lcdcont:inst1|shifter:myshift_high|qout[8] lcdcont:inst1|high[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "2.337 ns" { lcdcont:inst1|shifter:myshift_high|qout[8] lcdcont:inst1|high[8] } { 0.000ns 2.057ns } { 0.000ns 0.280ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-17.749 ns - Smallest " "Info: - Smallest clock skew is -17.749 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 8.164 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50MHz\" to destination register is 8.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lcdcont:inst1\|clockdiv:div\|clock_int 2 REG LC_X12_Y3_N6 68 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N6; Fanout = 68; REG Node = 'lcdcont:inst1\|clockdiv:div\|clock_int'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int } "NODE_NAME" } } { "../LCD/lcd_zifu/clockdiv.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/clockdiv.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.051 ns) + CELL(0.918 ns) 8.164 ns lcdcont:inst1\|high\[8\] 3 REG LC_X13_Y6_N2 1 " "Info: 3: + IC(3.051 ns) + CELL(0.918 ns) = 8.164 ns; Loc. = LC_X13_Y6_N2; Fanout = 1; REG Node = 'lcdcont:inst1\|high\[8\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.969 ns" { lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } "NODE_NAME" } } { "../Creativity/lcdcont.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 134 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.34 % ) " "Info: Total cell delay = 3.375 ns ( 41.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.789 ns ( 58.66 % ) " "Info: Total interconnect delay = 4.789 ns ( 58.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.164 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.164 ns" { clk_50MHz clk_50MHz~combout lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } { 0.000ns 0.000ns 1.738ns 3.051ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 25.913 ns - Longest register " "Info: - Longest clock path from clock \"clk_50MHz\" to source register is 25.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns DPSK_shell:inst\|clk_div:comb_5\|qa\[4\] 2 REG LC_X10_Y5_N4 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N4; Fanout = 3; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qa\[4\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.876 ns) + CELL(0.511 ns) 6.582 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0~128 3 COMB LC_X11_Y5_N7 1 " "Info: 3: + IC(1.876 ns) + CELL(0.511 ns) = 6.582 ns; Loc. = LC_X11_Y5_N7; Fanout = 1; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0~128'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.387 ns" { DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.511 ns) 7.859 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0 4 COMB LC_X11_Y5_N5 39 " "Info: 4: + IC(0.766 ns) + CELL(0.511 ns) = 7.859 ns; Loc. = LC_X11_Y5_N5; Fanout = 39; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.777 ns) + CELL(1.294 ns) 12.930 ns DPSK_shell:inst\|clk_div:comb_5\|qb\[0\] 5 REG LC_X9_Y7_N2 4 " "Info: 5: + IC(3.777 ns) + CELL(1.294 ns) = 12.930 ns; Loc. = LC_X9_Y7_N2; Fanout = 4; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qb\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.071 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.740 ns) 14.633 ns DPSK_shell:inst\|clk_div:comb_5\|Equal1 6 COMB LC_X9_Y7_N0 11 " "Info: 6: + IC(0.963 ns) + CELL(0.740 ns) = 14.633 ns; Loc. = LC_X9_Y7_N0; Fanout = 11; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal1'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.452 ns) + CELL(1.294 ns) 18.379 ns DPSK_shell:inst\|LCM_pre:comb_9\|wave_low\[0\] 7 REG LC_X10_Y7_N7 3 " "Info: 7: + IC(2.452 ns) + CELL(1.294 ns) = 18.379 ns; Loc. = LC_X10_Y7_N7; Fanout = 3; REG Node = 'DPSK_shell:inst\|LCM_pre:comb_9\|wave_low\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.746 ns" { DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] } "NODE_NAME" } } { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.343 ns) + CELL(0.914 ns) 20.636 ns DPSK_shell:inst\|LCM_pre:comb_9\|clk_ser 8 COMB LC_X10_Y7_N8 32 " "Info: 8: + IC(1.343 ns) + CELL(0.914 ns) = 20.636 ns; Loc. = LC_X10_Y7_N8; Fanout = 32; COMB Node = 'DPSK_shell:inst\|LCM_pre:comb_9\|clk_ser'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.257 ns" { DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser } "NODE_NAME" } } { "../Creativity/LCM_pre.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/LCM_pre.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.359 ns) + CELL(0.918 ns) 25.913 ns lcdcont:inst1\|shifter:myshift_high\|qout\[8\] 9 REG LC_X14_Y7_N9 2 " "Info: 9: + IC(4.359 ns) + CELL(0.918 ns) = 25.913 ns; Loc. = LC_X14_Y7_N9; Fanout = 2; REG Node = 'lcdcont:inst1\|shifter:myshift_high\|qout\[8\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.277 ns" { DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } "NODE_NAME" } } { "../LCD/lcd_zifu/shifter.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/shifter.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.639 ns ( 33.34 % ) " "Info: Total cell delay = 8.639 ns ( 33.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.274 ns ( 66.66 % ) " "Info: Total interconnect delay = 17.274 ns ( 66.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "25.913 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "25.913 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } { 0.000ns 0.000ns 1.738ns 1.876ns 0.766ns 3.777ns 0.963ns 2.452ns 1.343ns 4.359ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.511ns 1.294ns 0.740ns 1.294ns 0.914ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.164 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.164 ns" { clk_50MHz clk_50MHz~combout lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } { 0.000ns 0.000ns 1.738ns 3.051ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "25.913 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "25.913 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } { 0.000ns 0.000ns 1.738ns 1.876ns 0.766ns 3.777ns 0.963ns 2.452ns 1.343ns 4.359ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.511ns 1.294ns 0.740ns 1.294ns 0.914ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "../LCD/lcd_zifu/shifter.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/LCD/lcd_zifu/shifter.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "../Creativity/lcdcont.vhd" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/lcdcont.vhd" 134 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.337 ns" { lcdcont:inst1|shifter:myshift_high|qout[8] lcdcont:inst1|high[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "2.337 ns" { lcdcont:inst1|shifter:myshift_high|qout[8] lcdcont:inst1|high[8] } { 0.000ns 2.057ns } { 0.000ns 0.280ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "8.164 ns" { clk_50MHz lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "8.164 ns" { clk_50MHz clk_50MHz~combout lcdcont:inst1|clockdiv:div|clock_int lcdcont:inst1|high[8] } { 0.000ns 0.000ns 1.738ns 3.051ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "25.913 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "25.913 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|LCM_pre:comb_9|wave_low[0] DPSK_shell:inst|LCM_pre:comb_9|clk_ser lcdcont:inst1|shifter:myshift_high|qout[8] } { 0.000ns 0.000ns 1.738ns 1.876ns 0.766ns 3.777ns 0.963ns 2.452ns 1.343ns 4.359ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.511ns 1.294ns 0.740ns 1.294ns 0.914ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_50MHz 85 " "Warning: Circuit may not operate. Detected 85 non-operational path(s) clocked by clock \"clk_50MHz\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DPSK_shell:inst\|modulate:comb_6\|phase_table:comb_11\|qout\[0\] DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_4\|out1 clk_50MHz 16.456 ns " "Info: Found hold time violation between source pin or register \"DPSK_shell:inst\|modulate:comb_6\|phase_table:comb_11\|qout\[0\]\" and destination pin or register \"DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_4\|out1\" for clock \"clk_50MHz\" (Hold time is 16.456 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "17.861 ns + Largest " "Info: + Largest clock skew is 17.861 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz destination 28.918 ns + Longest register " "Info: + Longest clock path from clock \"clk_50MHz\" to destination register is 28.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns DPSK_shell:inst\|clk_div:comb_5\|qa\[4\] 2 REG LC_X10_Y5_N4 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N4; Fanout = 3; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qa\[4\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.876 ns) + CELL(0.511 ns) 6.582 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0~128 3 COMB LC_X11_Y5_N7 1 " "Info: 3: + IC(1.876 ns) + CELL(0.511 ns) = 6.582 ns; Loc. = LC_X11_Y5_N7; Fanout = 1; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0~128'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.387 ns" { DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.511 ns) 7.859 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0 4 COMB LC_X11_Y5_N5 39 " "Info: 4: + IC(0.766 ns) + CELL(0.511 ns) = 7.859 ns; Loc. = LC_X11_Y5_N5; Fanout = 39; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.777 ns) + CELL(1.294 ns) 12.930 ns DPSK_shell:inst\|clk_div:comb_5\|qb\[0\] 5 REG LC_X9_Y7_N2 4 " "Info: 5: + IC(3.777 ns) + CELL(1.294 ns) = 12.930 ns; Loc. = LC_X9_Y7_N2; Fanout = 4; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qb\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.071 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(0.740 ns) 14.633 ns DPSK_shell:inst\|clk_div:comb_5\|Equal1 6 COMB LC_X9_Y7_N0 11 " "Info: 6: + IC(0.963 ns) + CELL(0.740 ns) = 14.633 ns; Loc. = LC_X9_Y7_N0; Fanout = 11; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal1'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.726 ns) + CELL(1.294 ns) 16.653 ns DPSK_shell:inst\|clk_div:comb_5\|qc\[0\] 7 REG LC_X9_Y7_N4 5 " "Info: 7: + IC(0.726 ns) + CELL(1.294 ns) = 16.653 ns; Loc. = LC_X9_Y7_N4; Fanout = 5; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qc\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.020 ns" { DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.953 ns) + CELL(0.914 ns) 18.520 ns DPSK_shell:inst\|clk_div:comb_5\|Equal2 8 COMB LC_X9_Y7_N8 8 " "Info: 8: + IC(0.953 ns) + CELL(0.914 ns) = 18.520 ns; Loc. = LC_X9_Y7_N8; Fanout = 8; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal2'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.867 ns" { DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(1.294 ns) 21.503 ns DPSK_shell:inst\|key_buffer:comb_8\|state.s2 9 REG LC_X6_Y7_N8 3 " "Info: 9: + IC(1.689 ns) + CELL(1.294 ns) = 21.503 ns; Loc. = LC_X6_Y7_N8; Fanout = 3; REG Node = 'DPSK_shell:inst\|key_buffer:comb_8\|state.s2'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 } "NODE_NAME" } } { "../Creativity/key_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/key_buffer.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.947 ns) + CELL(1.294 ns) 24.744 ns DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|pass 10 REG LC_X4_Y7_N2 21 " "Info: 10: + IC(1.947 ns) + CELL(1.294 ns) = 24.744 ns; Loc. = LC_X4_Y7_N2; Fanout = 21; REG Node = 'DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_11\|pass'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.241 ns" { DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass } "NODE_NAME" } } { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.256 ns) + CELL(0.918 ns) 28.918 ns DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_4\|out1 11 REG LC_X8_Y10_N1 1 " "Info: 11: + IC(3.256 ns) + CELL(0.918 ns) = 28.918 ns; Loc. = LC_X8_Y10_N1; Fanout = 1; REG Node = 'DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_4\|out1'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.174 ns" { DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.227 ns ( 38.82 % ) " "Info: Total cell delay = 11.227 ns ( 38.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.691 ns ( 61.18 % ) " "Info: Total interconnect delay = 17.691 ns ( 61.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "28.918 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "28.918 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } { 0.000ns 0.000ns 1.738ns 1.876ns 0.766ns 3.777ns 0.963ns 0.726ns 0.953ns 1.689ns 1.947ns 3.256ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.511ns 1.294ns 0.740ns 1.294ns 0.914ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50MHz source 11.057 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_50MHz\" to source register is 11.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_50MHz 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk_50MHz'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50MHz } "NODE_NAME" } } { "DPSK.bdf" "" { Schematic "C:/Documents and Settings/s/桌面/Newest/设计/DPSK/DPSK.bdf" { { 216 -104 64 232 "clk_50MHz" "" } { -24 56 120 -8 "clk_50MHz" "" } { 208 64 125 224 "clk_50MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns DPSK_shell:inst\|clk_div:comb_5\|qa\[8\] 2 REG LC_X10_Y5_N8 2 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y5_N8; Fanout = 2; REG Node = 'DPSK_shell:inst\|clk_div:comb_5\|qa\[8\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.914 ns) 6.362 ns DPSK_shell:inst\|clk_div:comb_5\|Equal0 3 COMB LC_X11_Y5_N5 39 " "Info: 3: + IC(1.253 ns) + CELL(0.914 ns) = 6.362 ns; Loc. = LC_X11_Y5_N5; Fanout = 39; COMB Node = 'DPSK_shell:inst\|clk_div:comb_5\|Equal0'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.167 ns" { DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 } "NODE_NAME" } } { "../Creativity/clk_div.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/clk_div.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.777 ns) + CELL(0.918 ns) 11.057 ns DPSK_shell:inst\|modulate:comb_6\|phase_table:comb_11\|qout\[0\] 4 REG LC_X8_Y10_N0 3 " "Info: 4: + IC(3.777 ns) + CELL(0.918 ns) = 11.057 ns; Loc. = LC_X8_Y10_N0; Fanout = 3; REG Node = 'DPSK_shell:inst\|modulate:comb_6\|phase_table:comb_11\|qout\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.695 ns" { DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } "NODE_NAME" } } { "../Creativity/phase_table.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_table.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.289 ns ( 38.79 % ) " "Info: Total cell delay = 4.289 ns ( 38.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.768 ns ( 61.21 % ) " "Info: Total interconnect delay = 6.768 ns ( 61.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.057 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "11.057 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } { 0.000ns 0.000ns 1.738ns 1.253ns 3.777ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "28.918 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "28.918 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } { 0.000ns 0.000ns 1.738ns 1.876ns 0.766ns 3.777ns 0.963ns 0.726ns 0.953ns 1.689ns 1.947ns 3.256ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.511ns 1.294ns 0.740ns 1.294ns 0.914ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.057 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "11.057 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } { 0.000ns 0.000ns 1.738ns 1.253ns 3.777ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" { } { { "../Creativity/phase_table.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_table.v" 8 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.250 ns - Shortest register register " "Info: - Shortest register to register delay is 1.250 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPSK_shell:inst\|modulate:comb_6\|phase_table:comb_11\|qout\[0\] 1 REG LC_X8_Y10_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N0; Fanout = 3; REG Node = 'DPSK_shell:inst\|modulate:comb_6\|phase_table:comb_11\|qout\[0\]'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } "NODE_NAME" } } { "../Creativity/phase_table.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/phase_table.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.280 ns) 1.250 ns DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_4\|out1 2 REG LC_X8_Y10_N1 1 " "Info: 2: + IC(0.970 ns) + CELL(0.280 ns) = 1.250 ns; Loc. = LC_X8_Y10_N1; Fanout = 1; REG Node = 'DPSK_shell:inst\|pass_buffer_8bit:u7\|pass_buffer:comb_4\|out1'" { } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 22.40 % ) " "Info: Total cell delay = 0.280 ns ( 22.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.970 ns ( 77.60 % ) " "Info: Total interconnect delay = 0.970 ns ( 77.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "1.250 ns" { DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } { 0.000ns 0.970ns } { 0.000ns 0.280ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "../Creativity/pass_buffer.v" "" { Text "C:/Documents and Settings/s/桌面/Newest/设计/Creativity/pass_buffer.v" 9 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "28.918 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "28.918 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[4] DPSK_shell:inst|clk_div:comb_5|Equal0~128 DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|clk_div:comb_5|qb[0] DPSK_shell:inst|clk_div:comb_5|Equal1 DPSK_shell:inst|clk_div:comb_5|qc[0] DPSK_shell:inst|clk_div:comb_5|Equal2 DPSK_shell:inst|key_buffer:comb_8|state.s2 DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } { 0.000ns 0.000ns 1.738ns 1.876ns 0.766ns 3.777ns 0.963ns 0.726ns 0.953ns 1.689ns 1.947ns 3.256ns } { 0.000ns 1.163ns 1.294ns 0.511ns 0.511ns 1.294ns 0.740ns 1.294ns 0.914ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.057 ns" { clk_50MHz DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "11.057 ns" { clk_50MHz clk_50MHz~combout DPSK_shell:inst|clk_div:comb_5|qa[8] DPSK_shell:inst|clk_div:comb_5|Equal0 DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] } { 0.000ns 0.000ns 1.738ns 1.253ns 3.777ns } { 0.000ns 1.163ns 1.294ns 0.914ns 0.918ns } "" } } { "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.250 ns" { DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } "NODE_NAME" } } { "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.0/quartus/bin/Technology_Viewer.qrui" "1.250 ns" { DPSK_shell:inst|modulate:comb_6|phase_table:comb_11|qout[0] DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1 } { 0.000ns 0.970ns } { 0.000ns 0.280ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
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