dpsk.map.eqn

用vhdl语言实现2DPSK数字传输

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--Y1_lcd_select is lcdcont:inst1|lcd:mylcd|lcd_select
--operation mode is normal

Y1_lcd_select_lut_out = Y1_state.code_address1 # Y1L95 # Y1_lcd_select & Y1L06;
Y1_lcd_select = DFFEAS(Y1_lcd_select_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--X1_clockout is lcdcont:inst1|clockdiv:div|clockout
--operation mode is normal

X1_clockout_lut_out = !X1_clockout;
X1_clockout = DFFEAS(X1_clockout_lut_out, clk_50MHz, VCC, , X1L05, , , , );


--W1_q[0] is DPSK_shell:inst|demodulate:comb_10|shift_detect:comb_4|my_shift_reg:comb_6|q[0]
--operation mode is normal

W1_q[0]_lut_out = W1L3Q;
W1_q[0] = DFFEAS(W1_q[0]_lut_out, J1L7, VCC, , , , , , );


--W1_q[4] is DPSK_shell:inst|demodulate:comb_10|shift_detect:comb_4|my_shift_reg:comb_6|q[4]
--operation mode is normal

W1_q[4]_lut_out = channel_choice_m & G1_q[0] # !channel_choice_m & (din_m2);
W1_q[4] = DFFEAS(W1_q[4]_lut_out, J1L7, VCC, , , , , , );


--V1_a is DPSK_shell:inst|demodulate:comb_10|shift_detect:comb_4|a
--operation mode is normal

V1_a = W1_q[0] $ W1_q[4];


--F1_q[0] is DPSK_shell:inst|generate_a:comb_7|q[0]
--operation mode is normal

F1_q[0]_lut_out = F1_q[1] & (!E1_state.s2);
F1_q[0] = DFFEAS(F1_q[0]_lut_out, D1L33, VCC, , , , , , );


--N2_out1 is DPSK_shell:inst|pass_buffer:u6|out1
--operation mode is normal

N2_out1_lut_out = V1_a;
N2_out1 = DFFEAS(N2_out1_lut_out, N01_pass, VCC, , , , , , );


--N01_pass is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|pass
--operation mode is normal

N01_pass_lut_out = !N01_pass;
N01_pass = DFFEAS(N01_pass_lut_out, !E2_state.s2, VCC, , , , , , );


--N2L1 is DPSK_shell:inst|pass_buffer:u6|dout~42
--operation mode is normal

N2L1 = N01_pass & N2_out1 # !N01_pass & (W1_q[0] $ W1_q[4]);


--N1_out1 is DPSK_shell:inst|pass_buffer:u5|out1
--operation mode is normal

N1_out1_lut_out = L1L1;
N1_out1 = DFFEAS(N1_out1_lut_out, N01_pass, VCC, , , , , , );


--L1L1 is DPSK_shell:inst|channel_choice:u1|q~8
--operation mode is normal

L1L1 = channel_choide_a & F1_q[0] # !channel_choide_a & (din_a2);


--N1L1 is DPSK_shell:inst|pass_buffer:u5|dout~42
--operation mode is normal

N1L1 = N01_pass & N1_out1 # !N01_pass & (L1L1);


--Y1_lcd_data[7] is lcdcont:inst1|lcd:mylcd|lcd_data[7]
--operation mode is normal

Y1_lcd_data[7]_lut_out = Y1_state.position;
Y1_lcd_data[7] = DFFEAS(Y1_lcd_data[7]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[6] is lcdcont:inst1|lcd:mylcd|lcd_data[6]
--operation mode is normal

Y1_lcd_data[6]_lut_out = !Y1L16;
Y1_lcd_data[6] = DFFEAS(Y1_lcd_data[6]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[5] is lcdcont:inst1|lcd:mylcd|lcd_data[5]
--operation mode is normal

Y1_lcd_data[5]_lut_out = Y1_state.setfunc;
Y1_lcd_data[5] = DFFEAS(Y1_lcd_data[5]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[4] is lcdcont:inst1|lcd:mylcd|lcd_data[4]
--operation mode is normal

Y1_lcd_data[4]_lut_out = Y1_state.setfunc # Y1L26 # Y1L62 & Y1L36;
Y1_lcd_data[4] = DFFEAS(Y1_lcd_data[4]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[3] is lcdcont:inst1|lcd:mylcd|lcd_data[3]
--operation mode is normal

Y1_lcd_data[3]_lut_out = Y1_state.home # Y1L46 # Y1L36 & Y1L82;
Y1_lcd_data[3] = DFFEAS(Y1_lcd_data[3]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[2] is lcdcont:inst1|lcd:mylcd|lcd_data[2]
--operation mode is normal

Y1_lcd_data[2]_lut_out = Y1L66 # Y1L36 & !Y1_count[1] & !Y1_count[2];
Y1_lcd_data[2] = DFFEAS(Y1_lcd_data[2]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[1] is lcdcont:inst1|lcd:mylcd|lcd_data[1]
--operation mode is normal

Y1_lcd_data[1]_lut_out = Y1_state.setmode # Y1L76 # Y1L36 & !Y1L14;
Y1_lcd_data[1] = DFFEAS(Y1_lcd_data[1]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--Y1_lcd_data[0] is lcdcont:inst1|lcd:mylcd|lcd_data[0]
--operation mode is normal

Y1_lcd_data[0]_lut_out = Y1_state.clear # Y1L86 # Y1L36 & !Y1L35;
Y1_lcd_data[0] = DFFEAS(Y1_lcd_data[0]_lut_out, X1_clockout, VCC, , !E3_state.s2, , , , );


--N01_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|out1
--operation mode is normal

N01_out1_lut_out = S1_qout[7];
N01_out1 = DFFEAS(N01_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[7] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7]
--operation mode is normal

S1_qout[7]_lut_out = !R1_s[4] & (U1_q[2] # U1_q[3] # !S1L01);
S1_qout[7] = DFFEAS(S1_qout[7]_lut_out, D1L63, VCC, , , , , , );


--N01L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_11|dout~12
--operation mode is normal

N01L1 = N01_pass & N01_out1 # !N01_pass & (S1_qout[7]);


--N9_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_10|out1
--operation mode is normal

N9_out1_lut_out = S1_qout[6];
N9_out1 = DFFEAS(N9_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[6] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[6]
--operation mode is normal

S1_qout[6]_lut_out = S1L11 & !S1L21 & (U1_q[4] $ H1_b_int[0]) # !S1L11 & (U1_q[4] $ !H1_b_int[0] # !S1L21);
S1_qout[6] = DFFEAS(S1_qout[6]_lut_out, D1L63, VCC, , , , , , );


--N9L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_10|dout~12
--operation mode is normal

N9L1 = N01_pass & N9_out1 # !N01_pass & (S1_qout[6]);


--N8_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_9|out1
--operation mode is normal

N8_out1_lut_out = S1_qout[5];
N8_out1 = DFFEAS(N8_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[5] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[5]
--operation mode is normal

S1_qout[5]_lut_out = S1L31 & !S1L41 & (U1_q[4] $ H1_b_int[0]) # !S1L31 & (U1_q[4] $ !H1_b_int[0] # !S1L41);
S1_qout[5] = DFFEAS(S1_qout[5]_lut_out, D1L63, VCC, , , , , , );


--N8L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_9|dout~12
--operation mode is normal

N8L1 = N01_pass & N8_out1 # !N01_pass & (S1_qout[5]);


--N7_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_8|out1
--operation mode is normal

N7_out1_lut_out = S1_qout[4];
N7_out1 = DFFEAS(N7_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[4] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[4]
--operation mode is normal

S1_qout[4]_lut_out = U1_q[0] & (U1_q[2] $ R1_s[4] $ !S1L51) # !U1_q[0] & (!U1_q[2] & !S1L51 # !R1_s[4]);
S1_qout[4] = DFFEAS(S1_qout[4]_lut_out, D1L63, VCC, , , , , , );


--N7L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_8|dout~12
--operation mode is normal

N7L1 = N01_pass & N7_out1 # !N01_pass & (S1_qout[4]);


--N6_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_7|out1
--operation mode is normal

N6_out1_lut_out = S1_qout[3];
N6_out1 = DFFEAS(N6_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[3] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[3]
--operation mode is normal

S1_qout[3]_lut_out = S1L61 & !S1L71 & (U1_q[4] $ H1_b_int[0]) # !S1L61 & (U1_q[4] $ !H1_b_int[0] # !S1L71);
S1_qout[3] = DFFEAS(S1_qout[3]_lut_out, D1L63, VCC, , , , , , );


--N6L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_7|dout~12
--operation mode is normal

N6L1 = N01_pass & N6_out1 # !N01_pass & (S1_qout[3]);


--N5_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_6|out1
--operation mode is normal

N5_out1_lut_out = S1_qout[2];
N5_out1 = DFFEAS(N5_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[2] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[2]
--operation mode is normal

S1_qout[2]_lut_out = S1L81 & !S1L91 & (U1_q[4] $ H1_b_int[0]) # !S1L81 & (U1_q[4] $ !H1_b_int[0] # !S1L91);
S1_qout[2] = DFFEAS(S1_qout[2]_lut_out, D1L63, VCC, , , , , , );


--N5L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_6|dout~12
--operation mode is normal

N5L1 = N01_pass & N5_out1 # !N01_pass & (S1_qout[2]);


--N4_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_5|out1
--operation mode is normal

N4_out1_lut_out = S1_qout[1];
N4_out1 = DFFEAS(N4_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[1] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[1]
--operation mode is normal

S1_qout[1]_lut_out = S1L02 & !S1L12 & (U1_q[4] $ H1_b_int[0]) # !S1L02 & (U1_q[4] $ !H1_b_int[0] # !S1L12);
S1_qout[1] = DFFEAS(S1_qout[1]_lut_out, D1L63, VCC, , , , , , );


--N4L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_5|dout~12
--operation mode is normal

N4L1 = N01_pass & N4_out1 # !N01_pass & (S1_qout[1]);


--N3_out1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|out1
--operation mode is normal

N3_out1_lut_out = S1_qout[0];
N3_out1 = DFFEAS(N3_out1_lut_out, N01_pass, VCC, , , , , , );


--S1_qout[0] is DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[0]
--operation mode is normal

S1_qout[0]_lut_out = S1L22 & !S1L32 & (U1_q[4] $ H1_b_int[0]) # !S1L22 & (U1_q[4] $ !H1_b_int[0] # !S1L32);
S1_qout[0] = DFFEAS(S1_qout[0]_lut_out, D1L63, VCC, , , , , , );


--N3L1 is DPSK_shell:inst|pass_buffer_8bit:u7|pass_buffer:comb_4|dout~12
--operation mode is normal

N3L1 = N01_pass & N3_out1 # !N01_pass & (S1_qout[0]);


--Y1_state.code_address1 is lcdcont:inst1|lcd:mylcd|state.code_address1
--operation mode is normal

Y1_state.code_address1_lut_out = Y1_state.ini1 # Y1_state.code_address1 & (!Y1L65 # !Y1_count[3]);
Y1_state.code_address1 = DFFEAS(Y1_state.code_address1_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1_state.code_address2 is lcdcont:inst1|lcd:mylcd|state.code_address2
--operation mode is normal

Y1_state.code_address2_lut_out = Y1_state.ini2 # Y1_state.code_address2 & (!Y1L65 # !Y1_count[3]);
Y1_state.code_address2 = DFFEAS(Y1_state.code_address2_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1_state.write is lcdcont:inst1|lcd:mylcd|state.write
--operation mode is normal

Y1_state.write_lut_out = VCC;
Y1_state.write = DFFEAS(Y1_state.write_lut_out, X1_clockout, !E3_state.s2, , Y1_state.position, , , , );


--Y1L95 is lcdcont:inst1|lcd:mylcd|Select~748
--operation mode is normal

Y1L95 = Y1_state.code_address2 # Y1_state.write;


--Y1_state.home is lcdcont:inst1|lcd:mylcd|state.home
--operation mode is normal

Y1_state.home_lut_out = Y1_state.setmode # Y1_state.home & (!Y1L55);
Y1_state.home = DFFEAS(Y1_state.home_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1_state.setfunc is lcdcont:inst1|lcd:mylcd|state.setfunc
--operation mode is normal

Y1_state.setfunc_lut_out = Y1L65 & !Y1_count[3] & (Y1_state.setfunc # !Y1_state.warmup) # !Y1L65 & Y1_state.setfunc;
Y1_state.setfunc = DFFEAS(Y1_state.setfunc_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1_state.clear is lcdcont:inst1|lcd:mylcd|state.clear
--operation mode is normal

Y1_state.clear_lut_out = Y1_state.dispoff # Y1_state.clear & (!Y1L85 # !Y1L75);
Y1_state.clear = DFFEAS(Y1_state.clear_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1_state.dispoff is lcdcont:inst1|lcd:mylcd|state.dispoff
--operation mode is normal

Y1_state.dispoff_lut_out = Y1L18;
Y1_state.dispoff = DFFEAS(Y1_state.dispoff_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1_state.setmode is lcdcont:inst1|lcd:mylcd|state.setmode
--operation mode is normal

Y1_state.setmode_lut_out = Y1L38;
Y1_state.setmode = DFFEAS(Y1_state.setmode_lut_out, X1_clockout, !E3_state.s2, , , , , , );


--Y1L7 is lcdcont:inst1|lcd:mylcd|count[2]~602
--operation mode is normal

Y1L7 = !Y1_state.dispoff & !Y1_state.setmode;


--Y1L06 is lcdcont:inst1|lcd:mylcd|Select~749
--operation mode is normal

Y1L06 = Y1_state.home # Y1_state.setfunc # Y1_state.clear # !Y1L7;


--E3_state.s2 is DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_40|state.s2
--operation mode is normal

E3_state.s2_lut_out = E3_state.s1 & (!reset);
E3_state.s2 = DFFEAS(E3_state.s2_lut_out, X1_clockout, VCC, , , , , , );


--X1_\count:counter[12] is lcdcont:inst1|clockdiv:div|\count:counter[12]
--operation mode is normal

X1_\count:counter[12]_lut_out = X1L61;
X1_\count:counter[12] = DFFEAS(X1_\count:counter[12]_lut_out, clk_50MHz, VCC, , , , , , );


--X1_\count:counter[14] is lcdcont:inst1|clockdiv:div|\count:counter[14]
--operation mode is normal

X1_\count:counter[14]_lut_out = X1L81 & !X1L05;
X1_\count:counter[14] = DFFEAS(X1_\count:counter[14]_lut_out, clk_50MHz, VCC, , , , , , );


--X1_\count:counter[13] is lcdcont:inst1|clockdiv:div|\count:counter[13]
--operation mode is normal

X1_\count:counter[13]_lut_out = X1L91 & !X1L05;
X1_\count:counter[13] = DFFEAS(X1_\count:counter[13]_lut_out, clk_50MHz, VCC, , , , , , );


--X1_\count:counter[11] is lcdcont:inst1|clockdiv:div|\count:counter[11]
--operation mode is normal

X1_\count:counter[11]_lut_out = X1L12 & !X1L05;
X1_\count:counter[11] = DFFEAS(X1_\count:counter[11]_lut_out, clk_50MHz, VCC, , , , , , );


--X1L64 is lcdcont:inst1|clockdiv:div|reduce_nor~99
--operation mode is normal

X1L64 = X1_\count:counter[12] # !X1_\count:counter[11] # !X1_\count:counter[13] # !X1_\count:counter[14];


--X1_\count:counter[10] is lcdcont:inst1|clockdiv:div|\count:counter[10]
--operation mode is normal

X1_\count:counter[10]_lut_out = X1L32;
X1_\count:counter[10] = DFFEAS(X1_\count:counter[10]_lut_out, clk_50MHz, VCC, , , , , , );


--X1_\count:counter[9] is lcdcont:inst1|clockdiv:div|\count:counter[9]
--operation mode is normal

X1_\count:counter[9]_lut_out = X1L52;
X1_\count:counter[9] = DFFEAS(X1_\count:counter[9]_lut_out, clk_50MHz, VCC, , , , , , );


--X1_\count:counter[8] is lcdcont:inst1|clockdiv:div|\count:counter[8]
--operation mode is normal

X1_\count:counter[8]_lut_out = X1L72;
X1_\count:counter[8] = DFFEAS(X1_\count:counter[8]_lut_out, clk_50MHz, VCC, , , , , , );


--X1_\count:counter[7] is lcdcont:inst1|clockdiv:div|\count:counter[7]
--operation mode is normal

X1_\count:counter[7]_lut_out = X1L92;
X1_\count:counter[7] = DFFEAS(X1_\count:counter[7]_lut_out, clk_50MHz, VCC, , , , , , );