clk_div.sim.vwf

用vhdl语言实现2DPSK数字传输

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 10000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk_50MHz")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk_diff")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("clk_lcd")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("clk_phase")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk_50MHz")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 500000;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("clk_diff")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 378490.0;
		NODE
		{
			REPEAT = 22;
			LEVEL 1 FOR 54560.0;
			LEVEL 0 FOR 381920.0;
		}
		LEVEL 1 FOR 18950.0;
	}
}

TRANSITION_LIST("clk_lcd")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 51130.0;
		NODE
		{
			REPEAT = 182;
			LEVEL 1 FOR 6820.0;
			LEVEL 0 FOR 47740.0;
		}
		LEVEL 1 FOR 6820.0;
		LEVEL 0 FOR 12130.0;
	}
}

TRANSITION_LIST("clk_phase")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10210.0;
		NODE
		{
			REPEAT = 1464;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 6800.0;
		}
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 5290.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk_50MHz";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk_diff";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk_lcd";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clk_phase";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 18375;
	MASTER = TRUE;
}
;