dpsk.tan.rpt

用vhdl语言实现2DPSK数字传输

; Clock Setup: 'clk_50MHz'     ; N/A                                      ; None          ; 48.21 MHz ( period = 20.743 ns ) ; DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] ; DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] ; clk_50MHz  ; clk_50MHz ; 0            ;
; Clock Hold: 'clk_50MHz'      ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; DPSK_shell:inst|LCM_pre:comb_12|key_buffer:comb_42|state.s2                       ; lcdcont:inst1|shifter:myshift_low|qout[1]                   ; clk_50MHz  ; clk_50MHz ; 116          ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                   ;                                                             ;            ;           ; 116          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------------------------------------+-------------------------------------------------------------+------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM1270T144C5      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_50MHz       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_50MHz'                                                                                                                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------+-------------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                              ; To                                                          ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------+-------------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 48.21 MHz ( period = 20.743 ns )                    ; DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] ; DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] ; clk_50MHz  ; clk_50MHz ; None                        ; None                      ; 7.372 ns                ;
; N/A                                     ; 48.79 MHz ( period = 20.496 ns )                    ; DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[4] ; DPSK_shell:inst|LCM_pre:comb_12|wave_low[1]                 ; clk_50MHz  ; clk_50MHz ; None                        ; None                      ; 6.707 ns                ;
; N/A                                     ; 49.38 MHz ( period = 20.250 ns )                    ; DPSK_shell:inst|modulate:comb_9|phase_counter:comb_10|my_syn_counter:comb_10|q[1] ; DPSK_shell:inst|modulate:comb_9|phase_table:comb_11|qout[7] ; clk_50MHz  ; clk_50MHz ; None                        ; None                      ; 6.879 ns                ;
; N/A                                     ; 49.45 MHz ( period = 20.221 ns )                    ; lcdcont:inst1|shifter:myshift_high|qout[8]                                        ; lcdcont:inst1|high[8]                                       ; clk_50MHz  ; clk_50MHz ; None                        ; None                      ; 1.608 ns                ;
; N/A                                     ; 49.75 MHz ( period = 20.102 ns )                    ; lcdcont:inst1|shifter:myshift_low|qout[9]                                         ; lcdcont:inst1|low[9]                                        ; clk_50MHz  ; clk_50MHz ; None                        ; None                      ; 1.489 ns                ;