lcm.v

用vhdl语言实现2DPSK数字传输

module LCM(reset,clk_lcd,lock,wave_in,RW,RS,E,cont,data_out);
input clk_lcd,reset,lock;
input [4:0] wave_in;
output RW,RS,E;
output [7:0] data_out;
output cont;

reg RW,RS,en;
reg [7:0] data_out;
reg [4:0] wave_int;
reg [1:0] wave_low;
reg [1:0] wave_low1;
wire [7:0] wave_out;
reg [4:0] count;
reg [1:0] bit_alert;
wire clk0,clk1,alert,clk;
wire reset_count;
reg [3:0] state;

parameter
	warmup=4'b0000,wait_long0=4'b0001,clc=4'b0010,
	wait_long1=4'b0011,function_set=4'b0100,display_set=4'b0101,
	input_set=4'b0110,CGRAM_set=4'b0111,code_address=4'b1000,
	input_set1=4'b1001,DDRAM_set=4'b1010,wave_code=4'b1011;

assign cont=0;
assign clk1=clk0&&lock;
assign clk=clk1&&alert;
assign clk0=clk_lcd;
assign E=en&&clk;
assign reset_count=~((state==warmup)||(state==clc)||(state==CGRAM_set));


always @(posedge clk0)
begin
wave_int=wave_in;//采样;
case (wave_int)	//译码;
0:wave_low=0;
1:wave_low=0;
2:wave_low=0;
3:wave_low=0;
4:wave_low=0;
5:wave_low=0;
6:wave_low=0;
7:wave_low=0;
8:wave_low=1;
9:wave_low=1;
10:wave_low=1;
11:wave_low=1;
12:wave_low=1;
13:wave_low=1;
14:wave_low=1;
15:wave_low=1;
16:wave_low=2;
17:wave_low=2;
18:wave_low=2;
19:wave_low=2;
20:wave_low=2;
21:wave_low=2;
22:wave_low=2;
23:wave_low=2;
24:wave_low=3;
25:wave_low=3;
26:wave_low=3;
27:wave_low=3;
28:wave_low=3;
29:wave_low=3;
30:wave_low=3;
31:wave_low=3;
endcase
end

assign wave_out[1:0]=wave_low;
assign wave_out[7:2]=6'b001100;

always@(posedge clk0)
begin
wave_low1=wave_low;
end

xor (bit_alert[0],wave_low[0],wave_low1[0]);
xor (bit_alert[1],wave_low[1],wave_low1[1]);

or (alert,bit_alert[0],bit_alert[1]);

//lcm control state circle;
//state: warmup,wait_long0,clc,wait_long1,function_set,
//display_set,input_set,CGRAM_set,code_address,
//input_set1,DDRAM_set,wave_code;

always @(posedge clk)
begin
if(reset==0)	state=warmup;
case (state)
warmup:
	begin	
	RW=0;
	RS=0;
	en=1;
	data_out=8'b00000000;
	state=wait_long0;
	//reset_count=0;
	end
wait_long0:
	begin
	if(count==1) en=0;
	else if(count==31) state=clc;
	else state=wait_long0;
	end
clc:
	begin
	en=1;
	data_out=8'b00000001;
	state=wait_long1;
	//reset_count=0;
	end
wait_long1:
	begin
	if(count==1) en=0;
	else if(count==31) state=function_set;
	else state=wait_long1;
	end
function_set:
	begin
	en=1;
	data_out=8'b00110000;
	state=display_set;
	end
display_set:
	begin
	data_out=8'b00001000;
	state=input_set;
	end
input_set:
	begin
	data_out=8'b00000110;
	state=CGRAM_set;
	end
CGRAM_set:
	begin
	data_out=8'b01000000;
	state=code_address;
	//reset_count=0;
	end
code_address:
	begin
	RS=1;
	case (count)
	0:data_out=8'b00000111;
	1:data_out=8'b00001110;
	2:data_out=8'b00011000;
	3:data_out=8'b00010000;
	4:data_out=8'b00000000;
	5:data_out=8'b00000000;
	6:data_out=8'b00000000;
	7:data_out=8'b00000000;
	8:data_out=8'b00011100;
	9:data_out=8'b00001110;
	10:data_out=8'b00000011;
	11:data_out=8'b00000001;
	12:data_out=8'b00000000;
	13:data_out=8'b00000000;
	14:data_out=8'b00000000;
	15:data_out=8'b00000000;
	16:data_out=8'b00000000;
	17:data_out=8'b00000000;
	18:data_out=8'b00000000;
	19:data_out=8'b00011000;
	20:data_out=8'b00001100;
	21:data_out=8'b00000111;
	22:data_out=8'b00000011;
	23:data_out=8'b00000000;
	24:data_out=8'b00000000;
	25:data_out=8'b00000000;
	26:data_out=8'b00000000;
	27:data_out=8'b00000001;
	28:data_out=8'b00000011;
	29:data_out=8'b00001110;
	30:data_out=8'b00011100;
	31:data_out=8'b00000000;
	endcase
	if(count==31) state=input_set1;
	else state=code_address;
	end
input_set1:
	begin
	RS=0;
	data_out=8'b00000111;
	state=DDRAM_set;
	end
DDRAM_set:
	begin
	data_out=8'b10001111;	
	state=wave_code;
	end
wave_code:
	begin
	RS=1;
	data_out=wave_out;
	state=wave_code;
	end
endcase
end

always@(posedge clk0)
begin
if(reset_count==0) count=0;
else count=count+1;
end

endmodule