lcm_pre.v

用vhdl语言实现2DPSK数字传输

module LCM_pre(reset,clk_lcm_buf,clk_lcd_base,lock,wave_in,reset_pre,clk_ser,lock_pre,wave_out);
//这个模块用于调理LCM模块的时钟，它综合了琐存逻辑，
//wave_in波形的连贯性调整（异或逻辑）及波形-ascii码译码；
input reset,clk_lcm_buf,clk_lcd_base,lock;
input [4:0] wave_in;
output clk_ser;
output [1:0] wave_out;
output reset_pre;
output lock_pre;

reg [4:0] wave_int;
reg [1:0] wave_low;
reg [1:0] wave_low1;
wire [1:0] bit_alert;
wire alert;
wire clk0;

assign clk0=clk_lcd_base;

always @(posedge clk0)
begin
wave_int=wave_in;//采样;
case (wave_int)	//译码;
0:wave_low=0;
1:wave_low=0;
2:wave_low=0;
3:wave_low=0;
4:wave_low=0;
5:wave_low=0;
6:wave_low=0;
7:wave_low=0;
8:wave_low=1;
9:wave_low=1;
10:wave_low=1;
11:wave_low=1;
12:wave_low=1;
13:wave_low=1;
14:wave_low=1;
15:wave_low=1;
16:wave_low=2;
17:wave_low=2;
18:wave_low=2;
19:wave_low=2;
20:wave_low=2;
21:wave_low=2;
22:wave_low=2;
23:wave_low=2;
24:wave_low=3;
25:wave_low=3;
26:wave_low=3;
27:wave_low=3;
28:wave_low=3;
29:wave_low=3;
30:wave_low=3;
31:wave_low=3;
endcase
end

assign wave_out=wave_low;
//assign wave_out[7:2]=6'b000000;

always@(posedge clk0)
begin
wave_low1=wave_low;
end

xor (bit_alert[0],wave_low[0],wave_low1[0]);
xor (bit_alert[1],wave_low[1],wave_low1[1]);

or (alert,bit_alert[0],bit_alert[1]);

assign clk_ser=clk0 && alert;
key_buffer (.clk(clk_lcm_buf),.key_in(reset),.key_out(reset_pre));
key_buffer (.clk(clk_lcm_buf),.key_in(lock),.key_out(lock_pre));

endmodule