lcdcont.vhd

用vhdl语言实现2DPSK数字传输

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all;

entity lcdcont is
	generic ( asciiwidth : positive := 8);
	
	port (	lock		: in std_logic;
			clk 		: in std_logic;         -- 50MHz
			ser_clk		: in std_logic;			--2400Hz*8; 
		    reset 		: in std_logic;  
			ser_in	   : in std_logic_vector(1 downto 0);
		    data_out 	: out std_logic_vector(asciiwidth-1 downto 0); -- lcd data   
	        rw_out,cont 		: out std_logic;      	-- lcd read(1)/write(0) line
		    select_out 	: out std_logic;  		-- lcd select (0=data, 1=instruction)
		    enable_out 	: out std_logic;  		-- lcd enable line - must be pulsed!
			clk_lcm_buf : out std_logic		);
end lcdcont;

architecture structural of lcdcont is

component lcd
	port 
	(	clk        : in std_logic;
--		load		:in std_logic; 
		reset      : in std_logic;
		data_valid : in std_logic;    -- causes lcd to start new write cycle when high
--		data_in	   : in std_logic_vector(asciiwidth-1 downto 0);
		high,low	:in std_logic_vector(15 downto 0);
		lcd_data   : out std_logic_vector(asciiwidth-1 downto 0);
		lcd_select : out std_logic;
		lcd_rw     : out std_logic;
		lcd_enable : out std_logic;
		done       : out std_logic
	);  	-- set low during write cycle, high if ready for new data
		
end component;


component clockdiv
	port(
    	clockin : in std_logic;
    	clockout : out std_logic );
end component;

component shifter 
	port(--data	:in std_logic_vector(15 downto 0);
		reset,sr_in,clk	:in std_logic;
--		sl_in,sr_in,reset,clk:in std_logic;
--		mode	:in std_logic_vector(1 downto 0);
		qout	:buffer std_logic_vector(15 downto 0));
end component;

component cir_shifter 
	port(data_high,data_low	:in std_logic_vector(15 downto 0);
		load,clk	:in std_logic;
--		sl_in,sr_in,reset,clk:in std_logic;
--		mode	:in std_logic_vector(1 downto 0);
		qout	:buffer std_logic_vector(7 downto 0));
end component;

signal valid_int, enable_int, reset_int, done_int, rw_int : std_logic;
signal small_clk,half_small_clk : std_logic;
--signal ascii_code: std_logic_vector(asciiwidth-1 downto 0);
signal high,qout_int_high: std_logic_vector(15 downto 0);
signal low,qout_int_low: std_logic_vector(15 downto 0);

begin

clk_lcm_buf<=small_clk;
enable_out <= enable_int;
display : process(small_clk)
	begin
	if reset = '0' then
		valid_int <= '1';
	elsif rising_edge(small_clk) then
		if done_int = '1' then
			valid_int <= '1';	
		else
			valid_int <= '0';
		end if;
	end if;
end process;

--half_div: process(small_clk)
--	begin
--	if rising_edge(small_clk) then
--	half_small_clk<=not half_small_clk;
--	end if;
--end process;
cont<='0';

mylcd : lcd port map(
	clk => small_clk,
--	load=>lock,
	reset => reset,
	data_valid => valid_int,
--	data_in=>ascii_code,
	high=>high,low=>low,	--:in std_logic_vector(15 downto 0);
	lcd_data => data_out,
	lcd_select => select_out,
	lcd_rw => rw_out,
	lcd_enable => enable_int,
	done => done_int);


div : clockdiv port map(
	clockin => clk,
	clockout => small_clk);

myshift_high: shifter port map(
	reset=>reset,
	sr_in=>ser_in(1),
	clk=>ser_clk,
--	clk=>small_clk,
	qout=>qout_int_high);
myshift_low: shifter port map(
	reset=>reset,
	sr_in=>ser_in(0),
	clk=>ser_clk,
--	clk=>small_clk,
	qout=>qout_int_low);

	
--mycir_shift:cir_shifter port map(
--	data_high=>qout_int_high,
--	data_low=>qout_int_low,
--	load=>lock,
--	clk=>half_small_clk,
--	qout=>ascii_code);
toload: process(small_clk)
	begin
	if rising_edge(small_clk) then
		if(lock='0') then 
			high<=qout_int_high;
			low<=qout_int_low;
		end if;
	end if;
end process;


end structural;