dig_filter.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 29 行

module dig_filter(clk,din,out);
input clk,din;
output out;
reg [1:0] state;

wire reset;
wire set;
parameter start=2'b00,s1=2'b01,s0=2'b10,conver=2'b11;

assign set=(state==s1);
assign reset=(state==s0);

always @(posedge clk)
begin
case (state)
start: if (din==1) state<=s1;else state<=s0;
s1:if(din==1) state<=s1;else state<=conver;
s0:if(din==1) state<=conver;else state<=s0;
conver:if(din==1) state<=s1;else state<=s0;
default: state<=start;
endcase
end

my_trigger (.set(set),.reset(reset),.q(out));

endmodule