modulate.v

来自「用vhdl语言实现2DPSK数字传输」· Verilog 代码 · 共 29 行

module modulate(a,clk_phase,clk_dig,phase_out,phase_state);
input a,clk_phase,clk_dig;
output [7:0] phase_out;
output [4:0] phase_state;

reg [1:0] q;//find posedge of clk_dig;
wire clr;
reg [1:0] b_int;
wire b;
wire [4:0] s;
wire [7:0] phase_out;

assign phase_state=s;

diff_code (.a(a),.clk(clk_dig),.b(b));
phase_counter (.clk(clk_phase),.clr(clr),.syn(b_int[0]),.s(s));
phase_table (.clk(clk_phase),.address(s),.qout(phase_out));

always@(posedge clk_phase)
begin
b_int[0]=b_int[1];
b_int[1]=b;
q[0]=q[1];
q[1]=clk_dig;
end
assign clr=~((q[0]==0)&&(q[1]==1));

endmodule