s_right_shifter.v

verilog, TMSC6415 S单元代码

 
`timescale 1ns/10ps

module S_Right_Shifter(
src,
count,
unsign,
//Src2_Type,
result
);
//input Src2_Type;
input [39:0] src;
input [5:0] count;
input       unsign;
output [39:0] result;

reg  [39:0] result;

//always @(unsign or src or count or Src2_Type)
always @(unsign or src or count)
begin
  if(unsign) result=src>>count;
  else begin
    result={{64{src[39]}},src}>>count;//10.16 gongxiao
  end
end
endmodule