simd_adder16.v

来自「verilog, TMSC6415 S单元代码」· Verilog 代码 · 共 38 行

`resetall
`timescale 1ns/10ps

module simd_adder16 (Src1,Src2,cout_in,sum,Cout16,Cout15,Cout8,simd_8,compare_8);
output       Cout16;
output       Cout15;
output       Cout8;
output[15:0] sum;
input[15:0]  Src1;
input[15:0]  Src2;
input        cout_in;
input        simd_8;
input        compare_8;

wire[14:0] sum15;
wire cout_in_high;
//wire [7:0] sum_high10;


assign {Cout15,sum15}=Src1[14:0]+Src2[14:0]+cout_in;
assign cout_in_high=(Cout8&simd_8)|compare_8;

S_Adder_8 adder_8_0(
           .A  (Src1[7:0]),
           .B  (Src2[7:0]),
           .C  (cout_in),
           .D  (sum[7:0]),
           .Cout (Cout8)
);

S_Adder_8 adder_8_1(
           .A  (Src1[15:8]),
           .B  (Src2[15:8]),
           .C  (cout_in_high),
           .D  (sum[15:8]),
           .Cout (Cout16)
);
endmodule