📄 gate_control.tan.qmsg

📁 verilog写的数字频率计的控制模块,对程序进行控制
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f100hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f100hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f100hz destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"f100hz\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f100hz 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f100hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC8 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f100hz fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_2 4 REG LC6 2 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.73 % " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.27 % " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f100hz source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"f100hz\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f100hz 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f100hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC8 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f100hz fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC5 4 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.73 % " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.27 % " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register wire_1 register wire_2 33.56 MHz 29.8 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 33.56 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 29.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.200 ns - Smallest " "Info: - Smallest clock skew is -9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 8.500 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_16 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~106 2 COMB LOOP LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW1 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_2 3 REG LC6 2 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 17.700 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_16 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW1 fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_1 5 REG LC5 4 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f10hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f10hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f10hz destination 17.700 ns + Shortest register " "Info: + Shortest clock path from clock \"f10hz\" to destination register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f10hz 1 CLK PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 1; CLK Node = 'f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f10hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f10hz fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3
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💿 文件大小 96 K
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📂 所属分类 VHDL/FPGA/Verilog
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#verilog #数字频率计 #控制模块 #控制
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