gate_control.fit.summary

来自「verilog写的数字频率计的控制模块,对程序进行控制」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Mon Jul 17 20:29:19 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : gate_control
Top-level Entity Name : gate_control
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9 / 32 ( 28 % )
Total pins : 16 / 36 ( 44 % )
Device : EPM7032SLC44-5
Timing Models : Final