counter.tan.summary

来自「verilog写的频率计程序的计数模块,」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.800 ns
From           : EN
To             : F_OUT~reg0
From Clock     : 
To Clock       : F_IN
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 3.900 ns
From           : lpm_counter:Q0_rtl_0|dffs[0]
To             : Q0[0]
From Clock     : F_IN
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.200 ns
From           : EN
To             : F_OUT~reg0
From Clock     : 
To Clock       : F_IN
Failed Paths   : 0

Type           : Clock Setup: 'F_IN'
Slack          : N/A
Required Time  : None
Actual Time    : 140.85 MHz ( period = 7.100 ns )
From           : lpm_counter:Q0_rtl_0|dffs[0]
To             : lpm_counter:Q0_rtl_0|dffs[0]
From Clock     : F_IN
To Clock       : F_IN
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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