counter.fit.summary

来自「verilog写的频率计程序的计数模块,」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Mon Jul 10 20:34:33 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : counter
Top-level Entity Name : counter
Family : MAX7000S
Device : EPM7160SLC84-6
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 25 / 160 ( 15 % )
Total pins : 32 / 64 ( 50 % )