📄 ddr_sdram.srr
字号:
DQ[17] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[18] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[19] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[20] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[21] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[22] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[23] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[24] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[25] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[26] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[27] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[28] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[29] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[30] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[31] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[32] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[33] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[34] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[35] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[36] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[37] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[38] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[39] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[40] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[41] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[42] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[43] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[44] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[45] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[46] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[47] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[48] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[49] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[50] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[51] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[52] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[53] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[54] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[55] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[56] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[57] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[58] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[59] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[60] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[61] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[62] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
DQ[63] CLK200_inferred_clock [falling] 0.0 0.0 -0.4 -0.4
RESET_N CLK100_inferred_clock [rising] 0.0 0.0 -5.6 -5.6
=================================================================================================
Output Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
--------------------------------------------------------------------------------------------------
BA[0] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
BA[1] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
CAS_N CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
CKE CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
CMDACK CLK100_inferred_clock [rising] 0.0 6.1 5.0 -1.1
CS_N[0] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
CS_N[1] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[0] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[1] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[2] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[3] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[4] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[5] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[6] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[7] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[8] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[9] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[10] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[11] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[12] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[13] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[14] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[15] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[16] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[17] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[18] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[19] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[20] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[21] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[22] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[23] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[24] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[25] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[26] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[27] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[28] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[29] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[30] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[31] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[32] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[33] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[34] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[35] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[36] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[37] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[38] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[39] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[40] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[41] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[42] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[43] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[44] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[45] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[46] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[47] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[48] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[49] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[50] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[51] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[52] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[53] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[54] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[55] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[56] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[57] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[58] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[59] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[60] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[61] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[62] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[63] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[64] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[65] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[66] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[67] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[68] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[69] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[70] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[71] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[72] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[73] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[74] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[75] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[76] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[77] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[78] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[79] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
DATAOUT[80] CLK100_inferred_clock [rising] 0.0 5.9 5.0 -0.9
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -