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📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
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dffeas \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4 (
	.clk(\rvclk~inputclkctrl_outclk ),
	.d(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7_combout ),
	.asdata(vcc),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\rdctrl_logic|state.INCADR~q ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q ),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4 .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4 .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X26_Y21_N0
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15_combout  = \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q  & \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q  & ( !\rdctrl_logic|state.INCADR~q  ) # 
// !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q  & \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q  & ( \rdctrl_logic|state.INCADR~q  ) # \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q  & 
// !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q 

	.dataa(!\rdctrl_logic|state.INCADR~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q ),
	.dataf(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15 .lut_mask = 64'h0000FFFF5555AAAA;
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15 .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X26_Y21_N1
dffeas \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0 (
	.clk(\rvclk~inputclkctrl_outclk ),
	.d(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15_combout ),
	.asdata(vcc),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q ),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0 .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0 .power_up = "low";
// synopsys translate_on

// atom is at LABCELL_X25_Y21_N26
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11_combout  = !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11 .lut_mask = 64'hFFFFFFFF00000000;
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11 .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X25_Y21_N27
dffeas \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0] (
	.clk(\rvclk~inputclkctrl_outclk ),
	.d(\mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11_combout ),
	.asdata(vcc),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\rdctrl_logic|state.INCADR~q ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|rdptr_g [0]),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X26_Y21_N24
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8_combout  = \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q  & \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q  # 
// \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q  & !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q  & ( !\rdctrl_logic|state.INCADR~q  # \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q  ) # 
// !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q  & !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q  & ( \rdctrl_logic|state.INCADR~q  & !\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q  )

	.dataa(!\rdctrl_logic|state.INCADR~q ),
	.datab(gnd),
	.datac(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q ),
	.datad(gnd),
	.datae(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q ),
	.dataf(!\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8 .lut_mask = 64'h5050AFAF0000FFFF;
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8 .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X26_Y21_N25
dffeas \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1 (
	.clk(\rvclk~inputclkctrl_outclk ),
	.d(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8_combout ),
	.asdata(vcc),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q ),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1 .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1 .power_up = "low";
// synopsys translate_on

// atom is at FF_X25_Y21_N25
dffeas \mydcfifo|dcfifo_component|auto_generated|rdptr_g[1] (
	.clk(\rvclk~inputclkctrl_outclk ),
	.d(gnd),
	.asdata(\mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q ),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\rdctrl_logic|state.INCADR~q ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|rdptr_g [1]),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X24_Y22_N38
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3_combout  = !\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q  $ \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [0]

	.dataa(!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [0]),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3 .lut_mask = 64'hAA55AA55AA55AA55;
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3 .shared_arith = "off";
// synopsys translate_on

// atom is at LABCELL_X25_Y22_N32
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7_combout  = !\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q 

	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7 .lut_mask = 64'hFFFF0000FFFF0000;
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7 .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X25_Y22_N33
dffeas \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7 (
	.clk(\trclk~inputclkctrl_outclk ),
	.d(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7_combout ),
	.asdata(vcc),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\wrctrl_logic|state.WRITE~q ),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q ),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7 .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7 .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X24_Y22_N16
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31_combout  = \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q  & ( !\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [1] $ 
// (!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [0] # !\wrctrl_logic|state.WRITE~q ) ) # !\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q  & ( \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [1] )

	.dataa(!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [0]),
	.datab(gnd),
	.datac(!\wrctrl_logic|state.WRITE~q ),
	.datad(!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [1]),
	.datae(gnd),
	.dataf(!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31 .extended_lut = "off";
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31 .lut_mask = 64'h00FF00FF05FA05FA;
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31 .shared_arith = "off";
// synopsys translate_on

// atom is at FF_X24_Y22_N17
dffeas \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1] (
	.clk(\trclk~inputclkctrl_outclk ),
	.d(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31_combout ),
	.asdata(vcc),
	.clrn(!\reset~inputclkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [1]),
	.prn(vcc));
// synopsys translate_off
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1] .is_wysiwyg = "true";
defparam \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1] .power_up = "low";
// synopsys translate_on

// atom is at MLABCELL_X24_Y22_N36
stratixiii_lcell_comb \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[3]~32 (
// Equation(s):
// \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[3]~32_combout  = \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [0] & ( \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [3] ) # 
// !\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [0] & ( !\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [3] $ (!\mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q  # !\wrctrl_logic|state.WRITE~q  # 
// \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a [1]) )

	.dataa(!\mydcfifo|dcfifo_component|auto_genera
上一页 1 2 3 45
💿 文件大小 908 K
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📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#alteral #VERILOG #DCFIFO #FPGA
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