an_dcfifo_top.vo

来自「alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 」· VO 代码 · 共 1,449 行 · 第 1/5 页

VO
1,449 行
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	.o(\q[0]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[0]~output .bus_hold = "false";
defparam \q[0]~output .open_drain_output = "false";
defparam \q[0]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y21_N82
stratixiii_io_obuf \q[1]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [1]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[1]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[1]~output .bus_hold = "false";
defparam \q[1]~output .open_drain_output = "false";
defparam \q[1]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y17_N113
stratixiii_io_obuf \q[2]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [2]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[2]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[2]~output .bus_hold = "false";
defparam \q[2]~output .open_drain_output = "false";
defparam \q[2]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y21_N20
stratixiii_io_obuf \q[3]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [3]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[3]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[3]~output .bus_hold = "false";
defparam \q[3]~output .open_drain_output = "false";
defparam \q[3]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y17_N82
stratixiii_io_obuf \q[4]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [4]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[4]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[4]~output .bus_hold = "false";
defparam \q[4]~output .open_drain_output = "false";
defparam \q[4]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y21_N20
stratixiii_io_obuf \q[5]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [5]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[5]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[5]~output .bus_hold = "false";
defparam \q[5]~output .open_drain_output = "false";
defparam \q[5]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y19_N20
stratixiii_io_obuf \q[6]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [6]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[6]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[6]~output .bus_hold = "false";
defparam \q[6]~output .open_drain_output = "false";
defparam \q[6]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y16_N64
stratixiii_io_obuf \q[7]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [7]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[7]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[7]~output .bus_hold = "false";
defparam \q[7]~output .open_drain_output = "false";
defparam \q[7]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y21_N82
stratixiii_io_obuf \q[8]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [8]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[8]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[8]~output .bus_hold = "false";
defparam \q[8]~output .open_drain_output = "false";
defparam \q[8]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y29_N33
stratixiii_io_obuf \q[9]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [9]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[9]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[9]~output .bus_hold = "false";
defparam \q[9]~output .open_drain_output = "false";
defparam \q[9]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y21_N113
stratixiii_io_obuf \q[10]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [10]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[10]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[10]~output .bus_hold = "false";
defparam \q[10]~output .open_drain_output = "false";
defparam \q[10]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y20_N113
stratixiii_io_obuf \q[11]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [11]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[11]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[11]~output .bus_hold = "false";
defparam \q[11]~output .open_drain_output = "false";
defparam \q[11]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y19_N51
stratixiii_io_obuf \q[12]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [12]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[12]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[12]~output .bus_hold = "false";
defparam \q[12]~output .open_drain_output = "false";
defparam \q[12]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y19_N113
stratixiii_io_obuf \q[13]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [13]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[13]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[13]~output .bus_hold = "false";
defparam \q[13]~output .open_drain_output = "false";
defparam \q[13]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y20_N51
stratixiii_io_obuf \q[14]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [14]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[14]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[14]~output .bus_hold = "false";
defparam \q[14]~output .open_drain_output = "false";
defparam \q[14]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y21_N113
stratixiii_io_obuf \q[15]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [15]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[15]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[15]~output .bus_hold = "false";
defparam \q[15]~output .open_drain_output = "false";
defparam \q[15]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y20_N20
stratixiii_io_obuf \q[16]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [16]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[16]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[16]~output .bus_hold = "false";
defparam \q[16]~output .open_drain_output = "false";
defparam \q[16]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X0_Y22_N33
stratixiii_io_obuf \q[17]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [17]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[17]~output_o ),
	.obar());
// synopsys translate_off
defparam \q[17]~output .bus_hold = "false";
defparam \q[17]~output .open_drain_output = "false";
defparam \q[17]~output .shift_series_termination_control = "false";
// synopsys translate_on

// atom is at IOOBUF_X53_Y17_N20
stratixiii_io_obuf \q[18]~output (
	.i(\myram|altsyncram_component|auto_generated|q_a [18]),
	.oe(vcc),
	.dynamicterminationcontrol(gnd),
	.seriesterminationcontrol(14'b00000000000000),
	.parallelterminationcontrol(14'b00000000000000),
	.devoe(devoe),
	.o(\q[18]~output_o ),
	.obar());
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an_dcfifo_top.vo - 源码说明

本页面展示了「alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输」中的 an_dcfifo_top.vo 源码文件，采用 VO 编程语言编写，共 1,449 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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