an_dcfifo_top.vo

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

// DATE "11/09/2007 12:05:47"

// 
// Device: Altera EP3SE50F484C2 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module an_dcfifo_top (
	trclk,
	reset,
	rvclk,
	word_count,
	q);
input 	trclk;
input 	reset;
input 	rvclk;
output 	[8:0] word_count;
output 	[31:0] q;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("an_dcfifo_top_v.sdo");
// synopsys translate_on

wire \rvclk~input_o ;
wire \reset~input_o ;
wire \trclk~input_o ;
wire \mydcfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe13|dffe14a[1]~feeder_combout ;
wire \word_count[0]~output_o ;
wire \word_count[1]~output_o ;
wire \word_count[2]~output_o ;
wire \word_count[3]~output_o ;
wire \word_count[4]~output_o ;
wire \word_count[5]~output_o ;
wire \word_count[6]~output_o ;
wire \word_count[7]~output_o ;
wire \word_count[8]~output_o ;
wire \q[0]~output_o ;
wire \q[1]~output_o ;
wire \q[2]~output_o ;
wire \q[3]~output_o ;
wire \q[4]~output_o ;
wire \q[5]~output_o ;
wire \q[6]~output_o ;
wire \q[7]~output_o ;
wire \q[8]~output_o ;
wire \q[9]~output_o ;
wire \q[10]~output_o ;
wire \q[11]~output_o ;
wire \q[12]~output_o ;
wire \q[13]~output_o ;
wire \q[14]~output_o ;
wire \q[15]~output_o ;
wire \q[16]~output_o ;
wire \q[17]~output_o ;
wire \q[18]~output_o ;
wire \q[19]~output_o ;
wire \q[20]~output_o ;
wire \q[21]~output_o ;
wire \q[22]~output_o ;
wire \q[23]~output_o ;
wire \q[24]~output_o ;
wire \q[25]~output_o ;
wire \q[26]~output_o ;
wire \q[27]~output_o ;
wire \q[28]~output_o ;
wire \q[29]~output_o ;
wire \q[30]~output_o ;
wire \q[31]~output_o ;
wire \rvclk~inputclkctrl_outclk ;
wire \rdctrl_logic|Add1~136_sumout ;
wire \reset~inputclkctrl_outclk ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~7_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|parity4~q ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~15_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~q ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g[0]~11_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~8_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a1~q ;
wire \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|_~3_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~7_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|parity7~q ;
wire \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[1]~31_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[3]~32_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a[2]~33_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a3~7_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a3~q ;
wire \mydcfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe13|dffe14a[3]~feeder_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a2~7_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a2~q ;
wire \mydcfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe13|dffe14a[2]~feeder_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~64_combout ;
wire \wrctrl_logic|Add0~120_sumout ;
wire \wrctrl_logic|state.IDLE~70_combout ;
wire \wrctrl_logic|state.IDLE~q ;
wire \wrctrl_logic|addr_o[0]~154_combout ;
wire \wrctrl_logic|Add0~121 ;
wire \wrctrl_logic|Add0~124_sumout ;
wire \wrctrl_logic|Add0~125 ;
wire \wrctrl_logic|Add0~128_sumout ;
wire \wrctrl_logic|Add0~129 ;
wire \wrctrl_logic|Add0~132_sumout ;
wire \wrctrl_logic|Add0~133 ;
wire \wrctrl_logic|Add0~136_sumout ;
wire \wrctrl_logic|Add0~137 ;
wire \wrctrl_logic|Add0~140_sumout ;
wire \wrctrl_logic|Add0~141 ;
wire \wrctrl_logic|Add0~144_sumout ;
wire \wrctrl_logic|Add0~145 ;
wire \wrctrl_logic|Add0~148_sumout ;
wire \wrctrl_logic|Equal0~34_combout ;
wire \wrctrl_logic|Equal0~35_combout ;
wire \wrctrl_logic|state.DONE~25_combout ;
wire \wrctrl_logic|state.DONE~q ;
wire \wrctrl_logic|Selector0~52_combout ;
wire \wrctrl_logic|state.WRITE~q ;
wire \mydcfifo|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe10|dffe11a[1]~feeder_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe10|dffe11a[2]~feeder_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~54_combout ;
wire \mydcfifo|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~0_combout ;
wire \rdctrl_logic|Selector0~44_combout ;
wire \rdctrl_logic|state.INCADR~q ;
wire \rdctrl_logic|state~138DUPLICATE_combout ;
wire \rdctrl_logic|state.IDLE~DUPLICATE_q ;
wire \rdctrl_logic|Selector1~61_combout ;
wire \rdctrl_logic|state.WAIT~q ;
wire \rdctrl_logic|word_count_o[0]~77_combout ;
wire \rdctrl_logic|Add1~137 ;
wire \rdctrl_logic|Add1~140_sumout ;
wire \rdctrl_logic|Add1~141 ;
wire \rdctrl_logic|Add1~144_sumout ;
wire \rdctrl_logic|Add1~145 ;
wire \rdctrl_logic|Add1~148_sumout ;
wire \rdctrl_logic|Add1~149 ;
wire \rdctrl_logic|Add1~152_sumout ;
wire \rdctrl_logic|Add1~153 ;
wire \rdctrl_logic|Add1~156_sumout ;
wire \rdctrl_logic|Add1~157 ;
wire \rdctrl_logic|Add1~160_sumout ;
wire \rdctrl_logic|Add1~161 ;
wire \rdctrl_logic|Add1~164_sumout ;
wire \rdctrl_logic|Add1~165 ;
wire \rdctrl_logic|Add1~168_sumout ;
wire \rdctrl_logic|state.WRITE~q ;
wire \trclk~inputclkctrl_outclk ;
wire \mydcfifo|dcfifo_component|auto_generated|rdptr_g1p|counter3a0~_wirecell_combout ;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \rdctrl_logic|addr_o[0]~_wirecell_combout ;
wire \rdctrl_logic|state.IDLE~q ;
wire \rdctrl_logic|state~138_combout ;
wire \rdctrl_logic|Add0~185_sumout ;
wire \rdctrl_logic|addr_o[0]~353_combout ;
wire \rdctrl_logic|Add0~186 ;
wire \rdctrl_logic|Add0~189_sumout ;
wire \rdctrl_logic|addr_o[1]~354_combout ;
wire \rdctrl_logic|addr_o[1]~_wirecell_combout ;
wire \rdctrl_logic|Add0~190 ;
wire \rdctrl_logic|Add0~193_sumout ;
wire \rdctrl_logic|addr_o[2]~355_combout ;
wire \rdctrl_logic|addr_o[2]~_wirecell_combout ;
wire \rdctrl_logic|Add0~194 ;
wire \rdctrl_logic|Add0~197_sumout ;
wire \rdctrl_logic|addr_o[0]~352_combout ;
wire \rdctrl_logic|addr_o[3]~356_combout ;
wire \rdctrl_logic|addr_o[3]~_wirecell_combout ;
wire \rdctrl_logic|Add0~198 ;
wire \rdctrl_logic|Add0~201_sumout ;
wire \rdctrl_logic|addr_o[4]~357_combout ;
wire \rdctrl_logic|addr_o[4]~_wirecell_combout ;
wire \rdctrl_logic|Add0~202 ;
wire \rdctrl_logic|Add0~205_sumout ;
wire \rdctrl_logic|addr_o[5]~358_combout ;
wire \rdctrl_logic|addr_o[5]~_wirecell_combout ;
wire \rdctrl_logic|addr_o[6]~_wirecell_combout ;
wire \rdctrl_logic|state.WRITE~DUPLICATE_q ;
wire \rdctrl_logic|addr_o[0]~352DUPLICATE_combout ;
wire \rdctrl_logic|Add0~206 ;
wire \rdctrl_logic|Add0~209_sumout ;
wire \rdctrl_logic|addr_o[6]~359_combout ;
wire \rdctrl_logic|Add0~210 ;
wire \rdctrl_logic|Add0~213_sumout ;
wire \rdctrl_logic|addr_o[7]~360_combout ;
wire \rdctrl_logic|addr_o[7]~_wirecell_combout ;
wire [31:0] \myram|altsyncram_component|auto_generated|q_a ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe13|dffe14a ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe13|dffe15a ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe10|dffe11a ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe10|dffe12a ;
wire [31:0] \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|wrptr_gp|counter8a ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|delayed_wrptr_g ;
wire [2:0] \mydcfifo|dcfifo_component|auto_generated|ram_address_a ;
wire [2:0] \mydcfifo|dcfifo_component|auto_generated|ram_address_b ;
wire [3:0] \mydcfifo|dcfifo_component|auto_generated|rdptr_g ;
wire [7:0] \wrctrl_logic|addr_o ;
wire [7:0] \rdctrl_logic|addr_o ;
wire [8:0] \rdctrl_logic|word_count_o ;
wire [31:0] \myrom|altsyncram_component|auto_generated|q_a ;

wire [17:0] \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [17:0] \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ;
wire [35:0] \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus ;
wire [35:0] \myrom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \myram|altsyncram_component|auto_generated|q_a [0] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \myram|altsyncram_component|auto_generated|q_a [1] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \myram|altsyncram_component|auto_generated|q_a [2] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \myram|altsyncram_component|auto_generated|q_a [3] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \myram|altsyncram_component|auto_generated|q_a [4] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \myram|altsyncram_component|auto_generated|q_a [5] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \myram|altsyncram_component|auto_generated|q_a [6] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \myram|altsyncram_component|auto_generated|q_a [7] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];
assign \myram|altsyncram_component|auto_generated|q_a [8] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8];
assign \myram|altsyncram_component|auto_generated|q_a [9] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [9];
assign \myram|altsyncram_component|auto_generated|q_a [10] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [10];
assign \myram|altsyncram_component|auto_generated|q_a [11] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [11];
assign \myram|altsyncram_component|auto_generated|q_a [12] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [12];
assign \myram|altsyncram_component|auto_generated|q_a [13] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [13];
assign \myram|altsyncram_component|auto_generated|q_a [14] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [14];
assign \myram|altsyncram_component|auto_generated|q_a [15] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [15];
assign \myram|altsyncram_component|auto_generated|q_a [16] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [16];
assign \myram|altsyncram_component|auto_generated|q_a [17] = \myram|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [17];

assign \myram|altsyncram_component|auto_generated|q_a [18] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0];
assign \myram|altsyncram_component|auto_generated|q_a [19] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [1];
assign \myram|altsyncram_component|auto_generated|q_a [20] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [2];
assign \myram|altsyncram_component|auto_generated|q_a [21] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [3];
assign \myram|altsyncram_component|auto_generated|q_a [22] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [4];
assign \myram|altsyncram_component|auto_generated|q_a [23] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [5];
assign \myram|altsyncram_component|auto_generated|q_a [24] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [6];
assign \myram|altsyncram_component|auto_generated|q_a [25] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [7];
assign \myram|altsyncram_component|auto_generated|q_a [26] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [8];
assign \myram|altsyncram_component|auto_generated|q_a [27] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [9];
assign \myram|altsyncram_component|auto_generated|q_a [28] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [10];
assign \myram|altsyncram_component|auto_generated|q_a [29] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [11];
assign \myram|altsyncram_component|auto_generated|q_a [30] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [12];
assign \myram|altsyncram_component|auto_generated|q_a [31] = \myram|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [13];

assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [0];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [1];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [2];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [3];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [4];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [5];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [6];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [7];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [8] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [8];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [9] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [9];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [10] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [10];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [11] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [11];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [12] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [12];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [13] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [13];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [14] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [14];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [15] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [15];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [16] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [16];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [17] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [17];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [18] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [18];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [19] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [19];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [20] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [20];
assign \mydcfifo|dcfifo_component|auto_generated|fifo_ram|q_b [21] = \mydcfifo|dcfifo_component|auto_generated|fifo_ram|ram_block9a0_PORTBDATAOUT_bus [21];