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📄 an_dcfifo_top_v.sdo

📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
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    (DELAY
      (ABSOLUTE
        (PORT i (1307:1307:1307) (1273:1273:1273))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[23\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1277:1277:1277) (1263:1263:1263))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[24\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1194:1194:1194) (1189:1189:1189))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[25\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1341:1341:1341) (1335:1335:1335))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[26\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1315:1315:1315) (1318:1318:1318))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[27\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1376:1376:1376) (1382:1382:1382))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[28\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1239:1239:1239) (1232:1232:1232))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[29\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1478:1478:1478) (1516:1516:1516))
        (IOPATH i o (1778:1778:1778) (1754:1754:1754))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[30\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1300:1300:1300) (1285:1285:1285))
        (IOPATH i o (1842:1842:1842) (1812:1812:1812))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_io_obuf")
    (INSTANCE q\[31\]\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1571:1571:1571) (1554:1554:1554))
        (IOPATH i o (1778:1778:1778) (1754:1754:1754))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_ena_reg")
    (INSTANCE rvclk\~inputclkctrl.extena_reg1)
    (DELAY
      (ABSOLUTE
        (PORT clk (376:376:376) (384:384:384))
        (IOPATH (posedge clk) q (156:156:156) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (34:34:34))
      (HOLD d (posedge clk) (10:10:10))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_and2")
    (INSTANCE rvclk\~inputclkctrl.outclk_and)
    (DELAY
      (ABSOLUTE
        (IOPATH IN1 Y (405:405:405) (432:432:432))
        (IOPATH IN2 Y (109:109:109) (140:140:140))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_and2")
    (INSTANCE rvclk\~inputclkctrl.enaout_and)
    (DELAY
      (ABSOLUTE
        (IOPATH IN2 Y (91:91:91) (102:102:102))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Add1\~136)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_ena_reg")
    (INSTANCE reset\~inputclkctrl.extena_reg1)
    (DELAY
      (ABSOLUTE
        (PORT clk (376:376:376) (384:384:384))
        (IOPATH (posedge clk) q (156:156:156) (167:167:167))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (34:34:34))
      (HOLD d (posedge clk) (10:10:10))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_and2")
    (INSTANCE reset\~inputclkctrl.outclk_and)
    (DELAY
      (ABSOLUTE
        (IOPATH IN1 Y (405:405:405) (432:432:432))
        (IOPATH IN2 Y (109:109:109) (140:140:140))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_and2")
    (INSTANCE reset\~inputclkctrl.enaout_and)
    (DELAY
      (ABSOLUTE
        (IOPATH IN2 Y (91:91:91) (102:102:102))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity4\~7)
    (DELAY
      (ABSOLUTE
        (IOPATH datad combout (425:425:425) (403:403:403))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity4)
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (PORT ena (1080:1080:1080) (1014:1014:1014))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a0\~15)
    (DELAY
      (ABSOLUTE
        (PORT dataa (531:531:531) (515:515:515))
        (PORT dataf (262:262:262) (250:250:250))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a0)
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~11)
    (DELAY
      (ABSOLUTE
        (PORT dataf (490:490:490) (470:470:470))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (PORT ena (833:833:833) (757:757:757))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a1\~8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (560:560:560) (538:538:538))
        (PORT datac (288:288:288) (275:275:275))
        (PORT dataf (263:263:263) (252:252:252))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a1)
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT asdata (600:600:600) (643:643:643))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (PORT ena (833:833:833) (757:757:757))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|_\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (344:344:344) (334:334:334))
        (IOPATH dataa combout (404:404:404) (372:372:372))
        (IOPATH datad combout (425:425:425) (403:403:403))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|parity7\~7)
    (DELAY
      (ABSOLUTE
        (IOPATH datae combout (352:352:352) (345:345:345))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|parity7)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (PORT ena (871:871:871) (791:791:791))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[1\]\~31)
    (DELAY
      (ABSOLUTE
        (PORT dataa (272:272:272) (262:262:262))
        (PORT datac (361:361:361) (351:351:351))
        (PORT dataf (327:327:327) (316:316:316))
        (IOPATH dataa combout (404:404:404) (372:372:372))
        (IOPATH datac combout (232:232:232) (237:237:237))
        (IOPATH datad combout (425:425:425) (403:403:403))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[3\]\~32)
    (DELAY
      (ABSOLUTE
        (PORT dataa (344:344:344) (334:334:334))
        (PORT datab (274:274:274) (263:263:263))
        (PORT datac (372:372:372) (361:361:361))
        (PORT dataf (258:258:258) (248:248:248))
        (IOPATH dataa combout (404:404:404) (372:372:372))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (232:232:232) (237:237:237))
        (IOPATH datad combout (425:425:425) (403:403:403))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")

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