fast_to_slow_gate.do

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

transcript on
if {[file exists gate_work]} {
	vdel -lib gate_work -all
}
vlib gate_work
vmap work gate_work

vlog -vlog01compat -work work an_dcfifo_top.vo

vlog -vlog01compat -work work an_dcfifo_top_fast_to_slow.vt

vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L stratixiii_ver -L gate_work -L work an_dcfifo_top_vlg_vec_tst

do gate_wave.do
view structure
view signals
run -all