gate_wave.do

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /an_dcfifo_top_vlg_vec_tst/i1/reset
add wave -noupdate -divider {Trasmitting Domain}
add wave -noupdate -format Logic /an_dcfifo_top_vlg_vec_tst/i1/trclk
add wave -noupdate -divider {Receiving Domain}
add wave -noupdate -format Logic /an_dcfifo_top_vlg_vec_tst/i1/rvclk
add wave -noupdate -format Literal -radix unsigned /an_dcfifo_top_vlg_vec_tst/i1/word_count
add wave -noupdate -format Literal -radix hexadecimal /an_dcfifo_top_vlg_vec_tst/i1/q
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5020179 ps} 0}
configure wave -namecolwidth 437
configure wave -valuecolwidth 86
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {4954612 ps} {5212916 ps}