📄 an_dcfifo_top_fast_to_slow.vwf

📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
💻 VWF
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
{
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	RADIX = Hexadecimal;
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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DISPLAY_LINE
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}

DISPLAY_LINE
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}

DISPLAY_LINE
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}

DISPLAY_LINE
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	RADIX = Hexadecimal;
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}

DISPLAY_LINE
{
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	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
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}

DISPLAY_LINE
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}

DISPLAY_LINE
{
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	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
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	TREE_LEVEL = 1;
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}

DISPLAY_LINE
{
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}

DISPLAY_LINE
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}

DISPLAY_LINE
{
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	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
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	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "q[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
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	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "q[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 42;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "q[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 43;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "q[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 44;
	TREE_LEVEL = 1;
	PARENT = 13;
}

DISPLAY_LINE
{
	CHANNEL = "q[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 45;
	TREE_LEVEL = 1;
	PARENT = 13;
}

TIME_BAR
{
	TIME = 11250;
	MASTER = TRUE;
}
;
上一页 12
💿 文件大小 908 K
👤 上传用户 pore
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#alteral #VERILOG #DCFIFO #FPGA
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