📄 an_dcfifo_top_fast_to_slow.vwf

📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 1.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1\
print_row_height 100";
	DATA_OFFSET = 0.0;
	DATA_DURATION = 5200.0;
	SIMULATION_TIME = 5200.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

USER_TYPE("__state")
{
	VALUES = "Undefined", "state.RESET", "state.READ", "state.WRITE";
}

USER_TYPE("__read_control_logic:rdctrl_logic|state")
{
	VALUES = "Undefined", "state.IDLE", "state.READ_INCADR", "state.WRITE", "state.DONE";
}

USER_TYPE("__write_control_logic:wrctrl_logic|state")
{
	VALUES = "Undefined", "state.IDLE", "state.WRITE", "state.DONE", "state.INCADR", "state.WAIT";
}

SIGNAL("q")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 32;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("q[31]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[30]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[29]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[28]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[27]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[26]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[25]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[24]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[23]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[22]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[21]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[20]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[19]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[18]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[17]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[16]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("q[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "q";
}

SIGNAL("reset")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("rvclk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("trclk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("word_count")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 9;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("word_count[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

SIGNAL("word_count[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "word_count";
}

TRANSITION_LIST("q[31]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[30]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[29]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[28]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[27]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[26]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[25]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[24]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[23]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[22]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[21]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[20]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[19]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[18]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[17]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[16]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5200.0;
	}
}

TRANSITION_LIST("q[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2965.0;
		LEVEL 1 FOR 2235.0;
	}
}

TRANSITION_LIST("q[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1265.0;
		LEVEL 1 FOR 1700.0;
		LEVEL 0 FOR 1720.0;
		LEVEL 1 FOR 515.0;
	}
}

TRANSITION_LIST("q[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 405.0;
		LEVEL 1 FOR 860.0;
		LEVEL 0 FOR 860.0;
		LEVEL 1 FOR 840.0;
		LEVEL 0 FOR 860.0;
		LEVEL 1 FOR 860.0;
		LEVEL 0 FOR 515.0;
	}
}

TRANSITION_LIST("q[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 65.0;
		LEVEL 1 FOR 340.0;
		LEVEL 0 FOR 440.0;
		LEVEL 1 FOR 420.0;
		LEVEL 0 FOR 420.0;
		LEVEL 1 FOR 440.0;
		LEVEL 0 FOR 420.0;
		LEVEL 1 FOR 420.0;
		LEVEL 0 FOR 440.0;
		LEVEL 1 FOR 420.0;
		LEVEL 0 FOR 420.0;
		LEVEL 1 FOR 440.0;
		LEVEL 0 FOR 420.0;
		LEVEL 1 FOR 95.0;
12 下一页
💿 文件大小 908 K
👤 上传用户 pore
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#alteral #VERILOG #DCFIFO #FPGA
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