decoder.v

完成的是RS422信号的计数功能

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.


// Generated by Quartus II Version 5.0 (Build Build 171 11/03/2005)
// Created on Wed Dec 19 16:45:05 2007

//  Module Declaration
module Decoder
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	AChip, DClock, Cnt4X, Index, CamrTrg,Step1,Count
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input 	AChip	;
	input 	DClock	;
	input 	Cnt4X	;
	input 	Index	;
	input   [7:0] Step1  ;
	
	output 	CamrTrg	;
//	output 	[3:0] CntO	;
	output  [23:0] Count; 
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    wire    [7:0] Step1  ;
	reg		TrigTe		;
	reg		AHistr		;
	reg		ABXorTe		;
	reg		[23:0] CntTe	;
	reg     [7:0]  CNT     ;
	reg     [7:0]  PreStep ;
	reg     [7:0]  Step ;
	
	reg     [7:0] Temp;
//assign	CntO	= CntTe[3:0]	;
assign	CamrTrg	= TrigTe		;
assign  Count  	= CntTe    		; 
always		@(posedge  DClock)
	begin
	    //Temp = Step1;
		//PreStep<=Step1;
		//if(PreStep==Step1)
		//Step=Step;
		//else 
		//Step=Step1;		
		if (ABXorTe != Cnt4X)
			begin		
				if (Cnt4X == 1)
					begin
						if (AHistr == AChip)
							begin
//								Step	= Step	- 1'b1  ;
								CntTe	= CntTe - 1'b1	;
							end
						else
							begin
								CntTe	= CntTe + 1'b1	;
//								Step	= Step	+ 1'b1  ;
								if ((Step1&CntTe[7:0]) == Step1)
									TrigTe	= 1'b0	;
								else
									TrigTe	= 1'b1	;
							end		
					end
				else
					begin
						if (AHistr == AChip)
							begin
//								Step	= Step	+ 1'b1  ;
								CntTe	= CntTe + 1'b1	;
								if ((Step1&CntTe[7:0]) == Step1)
									TrigTe	= 1'b0	;
								else
									TrigTe	= 1'b1	;
							end
						else
							begin
//								Step	= Step	- 1'b1  ;
								CntTe	= CntTe - 1'b1	;
							end
					end

				AHistr	= AChip	;
				ABXorTe	= Cnt4X	;

				if (Index == 0)
					begin
						CntTe	= 1'b0	;								//	Home point
						TrigTe	= 1'b1	;
					end

			end
				
	end

endmodule

/*
always		@(negedge DClock)
	begin
				
		if (ABXorTe != Cnt4X)
			begin		
				if (Cnt4X == 1)
					begin
						if (AHistr == AChip)
							begin
								CntTe	= CntTe - 1'b1	;
								if (CntTe[1:0] == 0)
									TrigTe	= 1'b1	;
								else
									TrigTe	= 1'b0	;
							end
						else
							begin
								CntTe	= CntTe + 1'b1	;
								if (CntTe[4:0] == 0)
									TrigTe	= 1'b1	;
								else
									TrigTe	= 1'b0	;
							end		
					end
				else
					begin
						if (AHistr == AChip)
							begin
								CntTe	= CntTe + 1'b1	;
								if (CntTe[4:0] == 0)
									TrigTe	= 1'b1	;
								else
									TrigTe	= 1'b0	;
							end
						else
							begin
								CntTe	= CntTe - 1'b1	;
								if (CntTe[1:0] == 0)
									TrigTe	= 1'b1	;
								else
									TrigTe	= 1'b0	;
							end
					end

				AHistr	= AChip	;
				ABXorTe	= Cnt4X	;

				if (Index == 0)
					begin
						CntTe	= 1'b0	;								//	Home point
						TrigTe	= 1'b0	;
					end

			end
				
	end

endmodule

//----------------------------------------------------------------------//	5um/t
*/