sel.v

来自「完成的是RS422信号的计数功能」· Verilog 代码 · 共 33 行

module SEL(
iCLK,
SW,
Step
);
input iCLK;
input [2:0] SW;
wire  [2:0] SW;

output [7:0] Step ;
reg    [7:0] Step ;
always @(posedge iCLK)
	begin	
		case(SW)
			3'b000:
				Step<=8'b00000001;
			3'b001:
				Step<=8'b00000011;
			3'b010:
				Step<=8'b00000111;
			3'b011:
				Step<=8'b00001111;
			3'b100:
				Step<=8'b00011111;
			3'b101:
				Step<=8'b00111111;
			3'b110:
				Step<=8'b01111111;
			3'b111:
				Step<=8'b11111111;
		endcase
	end
endmodule