segctr.v

来自「完成的是RS422信号的计数功能」· Verilog 代码 · 共 63 行

module SEGCtr(
iCLK,
iRST,
iDIG,
oDIG,
SEL
);
input iCLK;
input iRST;
input [23:0] iDIG;

output [3:0] oDIG; 
output [5:0] SEL;

wire iRST;
wire [23:0] iDIG;

reg  [7:0]  oDIG;
reg  [7:0]  cnt;
reg  [5:0]  SEL;

always @(posedge iCLK )
begin
if(cnt!=32)
cnt<=cnt+1;
else 
cnt<=0;
case (cnt)
8'd0:
begin
SEL<=6'b000001;
oDIG<=iDIG[3:0];
end
8'd5:
begin
SEL<=6'b000010;
oDIG<=iDIG[7:4];
end
8'd10:
begin
SEL<=6'b000100;
oDIG<=iDIG[11:8];
end
8'd15:
begin
SEL<=6'b001000;
oDIG<=iDIG[15:12];
end
8'd20:
begin
SEL<=6'b010000;
oDIG<=iDIG[19:16];
end
8'd25:
begin
SEL<=6'b100000;
oDIG<=iDIG[23:20];
end
default:
SEL<=6'b000000; 
endcase
end 
endmodule