clock.v

来自「完成的是RS422信号的计数功能」· Verilog 代码 · 共 30 行

module CLOCK(
iCLK,
oCLK1,
oCLK2
);
input iCLK;

output oCLK1;
output oCLK2;

wire iCLK;
reg  CLK2;

reg [15:0] CNT;

assign oCLK1=iCLK;
assign oCLK2=CLK2;

always @(posedge iCLK)
	begin
		if(CNT==16000)
			begin
			CLK2<=~CLK2;
			CNT<=16'd0;
			end
		else
			CNT<=CNT+1'b1;
	end
endmodule