dec.v

来自「完成的是RS422信号的计数功能」· Verilog 代码 · 共 73 行

module Dec(
iCLK,
iRST,
iDIG,
oDIG,
SEL
);
input iCLK;
input iRST;
input [23:0] iDIG;

output [3:0] oDIG; 
output [5:0] SEL;

wire iRST;
wire [23:0] iDIG;
wire [3:0]  gewei,shiwei,baiwei,qianwei,wanwei,shiwanwei;

reg  [7:0]  oDIG;
reg  [2:0]  cnt;
reg  [5:0]  SEL;
//reg  [3:0]  gewei,shiwei,baiwei,qianwei,wanwei,shiwanwei;

assign shiwanwei=(iDIG/100000);
assign wanwei=(iDIG%100000)/10000;
assign qianwei=(iDIG%10000)/1000;
assign baiwei=(iDIG%1000)/100;
assign shiwei=(iDIG%100)/10;
assign gewei=iDIG%10;

always @(posedge iCLK )
begin
if(cnt!=3'd6)
	cnt<=cnt+1;
else 
	cnt<=0;
case (cnt)

3'b001:
begin
SEL<=6'b111110;
oDIG<=gewei;
end
3'b010:
begin
SEL<=6'b111101;
oDIG<=shiwei;
end
3'b011:
begin
SEL<=6'b111011;
oDIG<=baiwei;
end
3'b100:
begin
SEL<=6'b110111;
oDIG<=qianwei;
end
3'b101:
begin
SEL<=6'b101111;
oDIG<=wanwei;
end
3'b110:
begin
SEL<=6'b011111;
oDIG<=shiwanwei;
end
default:
SEL<=6'b111111; 
endcase
end 
endmodule