fp50hz.v

来自「verilog设计的4位频率计」· Verilog 代码 · 共 14 行

module fp50HZ(clkin,clkout);
input clkin;
output clkout;
reg clkout;
reg[7:0] qout;
always @(posedge clkin)
   begin
    if(qout==24)
     begin 
       qout<=0;clkout<=~clkout;
     end
    else qout<=qout+1;
   end
endmodule