choose.vhd

来自「基本计时（12进制」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY choose IS
	PORT(clk1,clk2: in std_logic;	
		 clkout: out std_logic);
END choose;

ARCHITECTURE behave of choose IS
begin	
	process(clk1,clk2)
	begin
		if clk2='1' then
			clkout<=clk2;
		elsif clk1='1' and clk2='0' then
			clkout<=clk1;
		else
			clkout<='0';
		end if;
	end process;
end behave;