setalarm.vhd

来自「基本计时（12进制」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY setalarm IS
	PORT(clkalarm,miaoset1,miaoset2,fenset1,fenset2: in std_logic;	
		 clkout: out std_logic);
END setalarm;

ARCHITECTURE behave of setalarm IS
begin	
	process(clkalarm,miaoset1,miaoset2,fenset1,fenset2)
	begin
		if miaoset1 ='1' and miaoset2='1' and fenset1='1' and fenset2='1' then
			clkout<='1';
		else clkout<='0';
		end if;
	end process;
end behave;