set.vhd

来自「基本计时（12进制」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY set IS
	PORT(miaoin,fenin,shiin,setmiao,setfen,setshi,Set: in std_logic;	
		 coutmiao,coutfen,coutshi: out std_logic);
END set;

ARCHITECTURE behave of set IS
begin	
	process(miaoin,fenin,shiin,Set,setmiao,setfen,setshi)
	begin
	if Set = '1' then
		coutmiao <= setmiao;
		coutfen <= setfen;
		coutshi <= setshi;
	else
		coutmiao <= miaoin;
		coutfen <= fenin;
		coutshi <= shiin;
	end if;

	end process;
end behave;