setalarm2.vhd

来自「基本计时（12进制」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY setalarm2 IS
	PORT(clkalarm,miaoalarm1,miao2alarm1,miaoalarm2,miao2alarm2,fenalarm1,fenalarm2,shiset: in std_logic;	
		 clkout: out std_logic);
END setalarm2;

ARCHITECTURE behave of setalarm2 IS
begin	
	process(clkalarm,miaoalarm1,miaoalarm2,miao2alarm1,miao2alarm2,fenalarm1,fenalarm2,shiset)
	begin
		if ((miaoalarm1 ='1' and miaoalarm2='1')or(miao2alarm1 ='1' and miaoalarm2 ='1')or(miaoalarm1='1' and miao2alarm1 ='1' and miao2alarm2 ='1')) and fenalarm1='1' and fenalarm2='1' and shiset='1'  then
			clkout<='1';
		else clkout<='0';
		end if;
	end process;
end behave;