dpll_h_tp.v.bak

这是基于verilog语言写的

module DPLL_H_tp;
reg kclock,reset;
reg[7:0] H;
wire idclock;

parameter dely=100;
DPLL_H  inst_DPLL_H(idclock,kclock,H,reset);

initial
begin kclock=1;H=2;reset=0;
#(dely*20) reset=1;
#(dely*20) H=3;
#(dely*20) H=6;
#(dely*20)$stop;
end

always #(dely/2) kclock=~kclock;

initial
$monitor($time,,,"kclock=%d,idclock=%d,H=%d,reset=%d", kclock,idclokc,H,reset);
endmodule