dpll_tp.txt

这是基于verilog语言写的

module DPLL_tp;
reg fin,kclock,reset;
reg[3:0] k;
reg[7:0] N;
reg[7:0] H;
wire fout,fout2;

parameter dely=100;
DPLL  inst_DPLL(fin,fout,fout2,kclock,reset,k,N,H);

initial
begin fin=0;kclock=0;reset=0;k=4;N=64;H=8;
#(dely*10) reset=1;
end

always #(dely/1.6) kclock=~kclock;
always #(dely/(6.4*10^(-12)));

initial
$monitor($time,,,"fin=%d,fout=%d,fout2=%d,kclock=%d,reset=%d,k=%d,N=%d,H=%d" ,fin,fout,fout2,kclock,reset,k,N,H);


endmodule






end

always#(dely/1.6)  kclock=~kclock;