dpll_two_tp.v

这是基于verilog语言写的

module DPLL_two_tp;
reg fout2,reset;
wire fout;

parameter dely=100;
DPLL_two  inst_DPLL_two(fout2,fout,reset);

initial
begin fout2=0;reset=0;
#(dely*20) reset=1;
#(dely*20)$stop;
end

always #(dely/2) fout2=~fout2;

initial
$monitor($time,,,"fout2=%d,fout=%d,reset=%d", fout2,fout,reset);
endmodule