dpll_4count_tp.v.bak

这是基于verilog语言写的

module DPLL_4count_tp;
reg idout,reset;
reg[7:0] N;
wire fout2;

parameter dely=100;
DPLL_4count  inst_DPLL_4count(fout2,idout,N,reset);

initial
begin idout=1;N=2;reset=0;
#(dely*20) reset=1;
#(dely*20) N=4;
#(dely*20) N=6;
#(dely*20)$stop;
end

always #(dely/2) idout=~idout;

initial
$monitor($time,,,"idout=%d,fout2=%d,N=%d,reset=%d", idout,fout2,N,reset);
endmodule