lab1_tp.txt

这是基于verilog语言写的

module lab1_tp;
    
reg cp,en,clrn,ldn,uord;
    
reg[7:0] data;
   
wire[7:0] out;
   
parameter DELY=100;
    
lab1 inst_lab1(cp,en,clrn,ldn,uord,out,data);
    

  initial
    
begin cp=0;en=1;uord=0;clrn=1;ldn=1;data=8'b11;
    
#(DELY*2)  en=0;
    
#(DELY*2)  en=1;
    
#(DELY*60) uord=1;
   
#(DELY*60) clrn=0;
   
#(DELY*2)  clrn=1;
    
#(DELY*2)  ldn=0;
    
#(DELY*2)  ldn=1;
   
#(DELY*20)$stop;
    
end
    
    
always #(DELY/2) cp=~cp;
  initial 
    
$monitor($time,,,"cp=%d  en=%d uord=%d clrd=%d ldn=%d out=%d",cp,en,uord,clrn,ldn,out);

endmodule