dpll_tp.v

这是基于verilog语言写的

module DPLL_tp;
reg fin,kclock,reset;
reg[3:0] k;
reg[7:0] N;
reg[7:0] H;
wire fout;

parameter dely=100;
DPLL  inst_DPLL(fin,fout,kclock,reset,k,N,H);

initial
begin fin=0;kclock=0;reset=0;k=3;N=64;H=8;
#(dely*10) reset=1;
#(dely*1000000) $stop;
end

always #(dely/2) kclock=~kclock;
always #(dely*420) fin=~fin;

initial
$monitor($time,,,"fin=%d,fout=%d,kclock=%d,reset=%d,k=%d,N=%d,H=%d" ,fin,fout,kclock,reset,k,N,H);

endmodule