alu.v

用verilog HDL代码编写的快速除法器

//快速除法器源代码 ,verilog 代码 的快速除法器
module divider(clk,reset,cal_reg,dividend,divisor,ratio,remainder,error);
input clk;
input reset;
input cal_reg;
input [7:0] dividend;
input [7:0] divisor;
output [7:0] ratio;
output [7:0] remainder;
output error;
reg calculating;
reg [7:0] shift_counter;
reg [7:0] ratio;
reg [7:0] div_counter;
reg [7:0] divisor_r;
reg [7:0] shifted_dividend;
reg [7:0] remainder;

wire withdraw =(divisor_r <(shifted_dividend <<1));
wire done = (divisor_r < dividend )&& ~error;
wire error =(dividend >divisor) || (dividend ==8'b0);
always @(posedge clk)
begin
if(reset||error)
shifted_dividend <=8'b0;
else if (cal_reg ||withdraw)
shifted_dividend <=dividend;
else if (calculating)
shifted_dividend <=shifted_dividend << 1;
end

always @(posedge clk)
begin
if(reset||error)
divisor_r <=8'b0;
else if (cal_reg )
divisor_r <=divisor;
else if (withdraw)
divisor_r <=divisor_r - shifted_dividend ;
end

always @(posedge clk)
begin
if(cal_reg || reset||error ||withdraw || ~calculating )
shift_counter <=8'b1;
else
shift_counter <=shift_counter<<1;
end

always @(posedge clk)
begin
if(cal_reg || reset||error )
div_counter <=8'b0;
else if (withdraw)
div_counter <=div_counter + shift_counter;
end
//---------------------------------------------------------------------------
//www.icwin.net
//---------------------------------------------------------------------------
always @(posedge clk)
begin
if(reset||error)
calculating <=1'b0;
else if (cal_reg )
calculating <=1'b1;
else if (done)
calculating <=1'b0;
end

always @(posedge clk)
begin
if(reset||error)
begin
remainder <=8'b0;
ratio <= 8'b0;
end
else if (done)
begin
remainder <=divisor_r;
ratio <= div_counter;
end
end
endmodule

module alu(alu_out,zero,dividend,divisor,alu_clk,opcode);
 output zero;
 output[7:0] alu_out;
 input[7:0]  dividend,divisor;
 input[2:0]  opcode;
 input alu_clk;
 reg[7:0] alu_out;

 parameter 	HLT= 3'b000,
		DIV= 3'b001,
		ADD= 3'b010,
		ANDD=3'b011,
		XORR=3'b100,
		LDA= 3'b101,
		STO= 3'b110,
		JMP= 3'b111;
 assign zero=!divisor;
 always@(posedge alu_clk)
	begin
		casex(opcode)
			HLT: alu_out<=divisor;
			DIV: begin
				divider div(.clk(alu_clk),.dividend(dividend),.divisor(divisor),.ratio(alu_out));
					end
			ADD: alu_out<=dividend+divisor;
			ANDD:alu_out<=dividend&divisor;
			XORR:alu_out<=dividend^divisor;
			LDA: alu_out<=dividend;
			STO: alu_out<=divisor;
			JMP: alu_out<=divisor;
			default:alu_out<=8'bxxxx_xxxx;
		endcase
	end
endmodule