reg_add.tan.qmsg

自己用VHDL写的并行乘法累加和元算

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum93\[8\] " "Info: Node \"sum93\[8\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 38 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 38 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum94\[8\] " "Info: Node \"sum94\[8\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 39 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 39 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum101\[9\] " "Info: Node \"sum101\[9\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 42 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 42 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[0\] " "Info: Node \"sum91\[0\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[0\] " "Info: Node \"sum92\[0\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[1\] " "Info: Node \"sum91\[1\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[1\] " "Info: Node \"sum92\[1\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[2\] " "Info: Node \"sum92\[2\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[2\] " "Info: Node \"sum91\[2\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[3\] " "Info: Node \"sum92\[3\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[3\] " "Info: Node \"sum91\[3\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[4\] " "Info: Node \"sum91\[4\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[4\] " "Info: Node \"sum92\[4\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[5\] " "Info: Node \"sum91\[5\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[5\] " "Info: Node \"sum92\[5\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[6\] " "Info: Node \"sum91\[6\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[6\] " "Info: Node \"sum92\[6\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[7\] " "Info: Node \"sum91\[7\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[7\] " "Info: Node \"sum92\[7\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum91\[8\] " "Info: Node \"sum91\[8\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "sum92\[8\] " "Info: Node \"sum92\[8\]\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 37 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "flag\$latch " "Info: Node \"flag\$latch\"" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 52 -1 0 } }  } 0}  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 52 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_regbt " "Info: Assuming node \"clk_regbt\" is an undefined clock" {  } { { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_regbt" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_regbt register result\[3\] register result\[15\] 189.5 MHz 5.277 ns Internal " "Info: Clock \"clk_regbt\" has Internal fmax of 189.5 MHz between source register \"result\[3\]\" and destination register \"result\[15\]\" (period= 5.277 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.002 ns + Longest register register " "Info: + Longest register to register delay is 5.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns result\[3\] 1 REG LCFF_X9_Y7_N15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y7_N15; Fanout = 2; REG Node = 'result\[3\]'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "" { result[3] } "NODE_NAME" } "" } } { "reg_add.vhd" "" { Text "E:/vhdl_exe/reg_add/reg_add.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.263 ns) + CELL(0.601 ns) 1.864 ns add~1828 2 COMB LCCOMB_X9_Y7_N20 2 " "Info: 2: + IC(1.263 ns) + CELL(0.601 ns) = 1.864 ns; Loc. = LCCOMB_X9_Y7_N20; Fanout = 2; COMB Node = 'add~1828'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "1.864 ns" { result[3] add~1828 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.926 ns add~1830 3 COMB LCCOMB_X9_Y7_N22 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.926 ns; Loc. = LCCOMB_X9_Y7_N22; Fanout = 2; COMB Node = 'add~1830'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "0.062 ns" { add~1828 add~1830 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.988 ns add~1832 4 COMB LCCOMB_X9_Y7_N24 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.988 ns; Loc. = LCCOMB_X9_Y7_N24; Fanout = 2; COMB Node = 'add~1832'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "0.062 ns" { add~1830 add~1832 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 2.050 ns add~1834 5 COMB LCCOMB_X9_Y7_N26 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 2.050 ns; Loc. = LCCOMB_X9_Y7_N26; Fanout = 2; COMB Node = 'add~1834'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "0.062 ns" { add~1832 add~1834 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 2.112 ns add~1836 6 COMB LCCOMB_X9_Y7_N28 2 " "Info: 6: + IC(0.000 ns) + CELL(0.062 ns) = 2.112 ns; Loc. = LCCOMB_X9_Y7_N28; Fanout = 2; COMB Node = 'add~1836'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "0.062 ns" { add~1834 add~1836 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 2.286 ns add~1838 7 COMB LCCOMB_X9_Y7_N30 2 " "Info: 7: + IC(0.000 ns) + CELL(0.174 ns) = 2.286 ns; Loc. = LCCOMB_X9_Y7_N30; Fanout = 2; COMB Node = 'add~1838'" {  } { { "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" "" { Report "E:/vhdl_exe/reg_add/db/reg_add_cmp.qrpt" Compiler "reg_add" "UNKNOWN" "V1" "E:/vhdl_exe/reg_add/db/reg_add.quartus_db" { Floorplan "E:/vhdl_exe/reg_add/" "" "0.174 ns" { add~1836 add~1838 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 2.348 ns add~1840 8 COMB LCCOMB_X9_Y6_N0 2 " "Info: 8: + IC(0.000 ns) + CELL(0.062 ns) = 2.348 ns; Loc. = LCCOMB_X9_Y6_N0; Fanout = 2; COMB Node = 'add~1840'" {  } { { "E:/vhdl_exe/reg_ad